TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 155

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA001
11.3
DVOCR<DVOCK> is output from DVO pin.
DVO pin outputs the "H" level.
at DVOCR<DVOCK>.
is cleared to "0", the frequency of the divider output is not the frequency set at DVOCR<DVOCK>.
the divider output frequency does not reach the expected value due to synchronization of the gear clock (fcgck) and
the low-frequency clock (fs).
Select the divider output frequency at DVOCR<DVOCK>.
The divider output is enabled by setting DVOCR<DVOEN> to "1". Then, The rectangular waves selected by
It is disabled by clearing DVOVR<DVOEN> to "0". And DVO pin keeps "H" level.
When the operation is changed to STOP or IDLE0/SLEEP0 mode, DVOCR<DVOEN> is cleared to "0" and the
The divider output source clock operates, regardless of the value of DVOCR<DVOEN>.
Therefore, the frequency of the first divider output after DVOCR<DVOEN> is set to "1" is not the frequency set
When the operation is changed to the software, STOP or IDLE0/SLEEP0 mode is activated and DVOCR<DVOEN>
When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL mode,
Function
Example:1.953 kHz pulse output (fcgck = 8.0 MHz)
Table 11-1 Divider Output Frequency (Example: fcgck = 8.0 MHz, fs = 32.768 kHz)
LD
DVOCK
00
01
10
11
TBTCR<DVOEN>
DVO output
(DVOCR), 0y00000100
Figure 11-2 Divider Output Timing
DV9CK = 0
15.625 k
1.953 k
3.906 k
7.813 k
NORMAL 1/2, IDLE 1/2 mode
Divider output timing chart
Divider output frequency [Hz]
Page 139
DV9CK = 1
Reserved
1.024 k
2.048 k
4.096 k
;DVOCK ← "00", DVOEN ← "1"
SLOW1/2, SLEEP1
Reserved
1.024 k
2.048 k
4.096 k
mode
TMP89FS60