TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 238

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

16.2
Control
RA001
UART0 status register
UART0 receive data buffer
UART0 transmit data buffer
UART0SR
(0x001D)
RD0BUF
(0x001E)
(0x001E)
TD0BUF
Note 1: TBFL is cleared to "0" automatically after an INTTXD0 interrupt request is generated, and is set to "1" when data is set to
Note 2: When a read instruction is executed on UART0SR, bit 4 is read as "0".
Note 3: When the STOP, IDLE0 or SLEEP0 mode is activated, each bit of UART0SR is cleared to "0" and the UART stops.
Note 1: When the STOP, IDLE0 or SLEEP0 mode is activated, the RD0BUF values become undefined. If received data is required,
Note 1: When the STOP, IDLE0 or SLEEP0 mode is activated, the TD0BUF values become undefined.
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
After reset
TD0BUF.
After reset
read it before activating the mode.
After reset
OERR
PERR
FERR
RBSY
RBFL
TBSY
TBFL
Parity error flag
Framing error flag
Overrun error flag
Receive busy flag
Receive buffer full flag
Transmit busy flag
Transmit buffer full flag
RD0DR7
TD0DR7
PERR
W
R
R
7
0
7
0
7
0
RD0DR6
TD0DR6
FERR
W
R
R
6
0
6
0
6
0
RD0DR5
TD0DR5
OERR
W
R
R
5
0
5
0
5
0
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0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
0:
1:
No parity error
Parity error
No framing error
Framing error
No overrrun error
Overrun error
Before receiving or end of receiving
On receiving
Receive buffer empty
Receive buffer full
Before transmission or end of transmission
On transmitting
Transmit buffer empty
Transmit buffer full (Transmit data writing is completed)
RD0DR4
TD0DR4
W
R
R
4
0
4
0
4
0
-
RD0DR3
TD0DR3
RBSY
W
R
R
3
0
3
0
3
0
RD0DR2
TD0DR2
RBFL
W
R
R
2
0
2
0
2
0
RD0DR1
TD0DR1
TBSY
W
R
R
1
0
1
0
1
0
TMP89FS60
RD0DR0
TD0DR0
TBFL
W
R
R
0
0
0
0
0
0