TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 31

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.3
2.3.1
2.3.2
System control register 1
(0x0FDC)
SYSCR1
System clock controller
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1".
XTOUT
XOUT
and an operation mode control circuit.
(SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and
the clock gear control register (CGCR).
XTIN
XIN
Configuration
Control
The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter
The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2
OUTEN
Read/Write
DV9CK
Bit Symbol
After reset
RELM
STOP
Clock generator
clock oscillation
High-frequency
clock oscillation
Low-frequency
Activates the STOP mode
Selects the STOP mode release
method
Selects the port output state in the
STOP mode
Selects the input clock to stage 9 of
the divider
circuit
circuit
STOP
R/W
7
0
Figure 2-3 System Clock Controller
RELM
R/W
6
0
Oscillation/stop control
fc
fs
(×1/4, ×1/2, ×1)
OUTEN
Clock gear
R/W
CGCR
5
0
Page 15
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
FCGCKSEL
Operate the CPU and the peripheral circuits
Stop the CPU and the peripheral circuits (activate the STOP mode)
Edge-sensitive release mode (Release the STOP mode at the rising edge
of the STOP mode release signal)
Level-sensitive release mode (Release the STOP mode at the "H" level of
the STOP mode release signal)
High impedance
Output hold
fcgck/2
fs/4
DV9CK
R/W
9
4
0
1/4
fcgck
WUCCR
TBTCR
R
3
1
-
System clock
Warm-up
generator
counter
Timing
WUCDR
DV9CK
R
2
0
-
SYSCR1
INTWUC interrupt request
Operation mode
control circuit
R
1
0
-
TMP89FS60
SYSCR2
R
0
0
-