TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 37

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB000
2.3.4.1
Note 1: When the operation is switched to the STOP mode during the warm-up for the oscillation enabled by the software, the
(1)
(2)
warm-up counter holds the value at the time, and restarts counting after the STOP mode is released. In this case, the
warm-up time at the release of the STOP mode becomes insufficient. Don't switch the operation to the STOP mode during
the warm-up for the oscillation enabled by the software.
Warm-up counter operation when the oscillation is enabled by the hardware
Clock that generates the main
system clock when the STOP
voltage becomes stable and the time after a reset is released before the oscillation by the high-frequency
clock oscillation circuit becomes stable.
warm-up counter reset signal is released. At this time, the CPU and the peripheral circuits are held in
the reset state.
lects the high-frequency clock (fc) as the input clock to the warm-up counter.
up counter, and the 14-stage counter starts counting the high-frequency clock (fc).
reset is released for the CPU and the peripheral circuits.
the oscillation becomes stable at the release of the STOP mode.
when the STOP mode is activated, is selected as the input clock for frequency division circuit, regardless
of WUCCR<WUCSEL>.
at WUCCR<WUCDIV> and set the warm-up time at WUCDR.
frequency division circuit.
the operation is restarted by an instruction that follows the STOP mode activation instruction.
mode is activated
The warm-up counter serves to secure the time after a power-on reset is released before the supply
When the power is turned on and the supply voltage exceeds the power-on reset release voltage, the
A reset signal initializes WUCCR<WUCSEL> to "0" and WUCCR<WUCDIV> to "11", which se-
When a reset is released for the warm-up counter, the high-frequency clock (fc) is input to the warm-
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and a
WUCDR is initialized to 0x66 after reset release, which makes the warm-up time 0x66 × 2
The warm-up counter serves to secure the time after the oscillation is enabled by the hardware before
The high-frequency clock (fc) or the low-frequency clock (fs), which generates the main system clock
Before the STOP mode is activated, select the division rate of the input clock to the warm-up counter
When the STOP mode is released, the 14-stage counter starts counting the input clock selected in the
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and
Note:The clock output from the oscillation circuit is used as the input clock to the warm-up counter.
When a power-on reset is released or a reset is released
When the STOP mode is released
The warm-up time contains errors because the oscillation frequency is unstable until the oscil-
lation circuit becomes stable.
fc
fs
<WUCSEL>
Don’t Care
Don't Care
WUCCR
<WUCDIV>
Page 21
WUCCR
00
01
10
11
00
01
10
11
Counter input
fc / 2
fc / 2
fs / 2
fs / 2
clock
fc / 2
fs / 2
fc
fs
2
3
2
3
2
2
2
2
2
2
2
2
6
7
8
9
6
7
8
9
/ fc to 255 x 2
/ fc to 255 x 2
/ fc to 255 x 2
/ fc to 255 x 2
/ fs to 255 x 2
/ fs to 255 x 2
/ fs to 255 x 2
/ fs to 255 x 2
Warm-up time
6
7
8
9
6
7
8
9
/ fc
/ fc
/ fc
/ fc
/ fs
/ fs
/ fs
/ fs
TMP89FS60
9
/fc[s].