TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 297

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA002
18.4.4.2
the stop condition is generated is t
pin is t
period must be 5/fcgck[s] or longer for the externally input clock, regardless of the SBI0CR1<SCK> setting.
which pulls down a clock pulse to low will, in the first place, invalidate the clock pulse of another master
device which generates a high-level clock pulse. Therefore, the master outputting the high level must detect
this to correspond to it.
even if there are two or more masters on the same bus.
In the master mode, the hold time when the start condition is generated is t
When SBI0CR2<PIN> is set to "1" in the slave mode, the time that elapses before the release of the SCL
In both the master and slave modes, the high level period must be 3/fcgck[s] or longer and the low level
In the I
The serial bus interface circuit has a clock synchronization function. This function ensures normal transfer
The example explains clock synchronization procedures when two masters simultaneously exist on a bus.
Note:There are cases where the HIGH period differs from t
SCL pin (Master 1)
SCL pin (Master 2)
SCL (Bus)
Clock synchronization
LOW
edge of the SCL pin becomes blunt due to the load capacity of the bus.
SCL output
2
SCL input
C bus, due to the structure of the pin, in order to drive a bus with a wired AND, a master device
[s].
Figure 18-8 Example of Clock Synchronization
a
Figure 18-6 SCL Output
Figure 18-7 SCL Input
Count reset
t
HIGH
HIGH
t
HIGH
[s].
Page 281
t
LOW
b
Wait
HIGH
c
Count start
selected at SBI0CR1<SCK> when the rising
t
LOW
t HIGH = m / fcgck
t LOW = n / fcgck
fscl = 1 / (t HIGH + t LOW )
1/fscl
t
t
HIGH
LOW
≥ 5 / fcgck
≥ 3 / fcgck
HIGH
Count reset
[s] and the setup time when
TMP89FS60