TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 245

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA001
PE
0
0
1
1
16.8.1.2
RTSEL
000
001
010
011
100
Figure 16-4 Fine Adjustment of Baud Rate Clock Using UART0CR2<RTSEL>
STBT
0
1
0
1
Figure 16-5 UART0DR Calculation Method (When BRG Is Set to fcgck)
formula shown in Figure 16-5. For example, to generate a basic baud rate of 38400 [baud] with fcgck=4
[MHz], calculate the set value of UART0DR for each setting of UART0CR2<RTSEL> and compensate the
calculated value to a positive number to obtain the generated baud rate as shown in Figure 16-6. Basically,
select the set value of UART0CR2<RTSEL> that has the smallest baud rate error from among the generated
baud rates. In Figure 16-6, the setting of UART0CR2<RTSEL>="0y010" has the smallest error among the
calculated baud rates, and thus the generated baud rate is 38095 [baud] (−0.79%) against the basic baud rate
of 38400 [baud].
The set value of UART0DR for an operating frequency and baud rate can be calculated using the calculation
Note:The error from the basic baud rate should be accurate to within ±3%. Even if the error is within ±3%,
Calculation of set values of UART0CR2<RTSEL> and UART0DR
Start
Start
Start
Start
16
16
15
15
17
1
the communication may fail due to factors such as frequency errors of external controllers (for example,
a personal computer) and oscillators and the load capacity of the communication pin.
Bit 0
Bit 0
Bit 0
Bit 0
16
17
15
16
17
2
Bit 1
Bit 1
Bit 1
Bit 1
16
16
15
15
17
3
Bit 2
Bit 2
Bit 2
Bit 2
16
17
15
16
17
4
RTSEL
000
001
010
011
100
Bit 3
Bit 3
Bit 3
Bit 3
16
16
15
15
17
5
Number of RT clocks
Transfer frame
Bit 4
Bit 4
Bit 4
Bit 4
UARTDR =
UARTDR =
UARTDR =
UARTDR =
UARTDR =
16
17
15
16
17
6
Page 229
UARTDR set value
Bit 5
Bit 5
Bit 5
Bit 5
16
16
15
15
17
7
16.5 A [baud]
15.5 A [baud]
16 A [baud]
15 A [baud]
17 A [baud]
Bit 6
Bit 6
Bit 6
Bit 6
fcgck [Hz]
fcgck [Hz]
fcgck [Hz]
fcgck [Hz]
fcgck [Hz]
16
17
15
16
17
8
Bit 7
Bit 7
Bit 7 Parity
Bit 7
16
16
15
15
17
9
Stop 1
Stop 1 Stop 2
Parity
10
16
17
15
16
17
1
1
1
1
1
Stop 1
Stop 1 Stop 2
11
16
16
15
15
17
12
16
17
15
16
17
*When BRG is set to fcgck
16.5 (UARTDR+1)
15.5 (UARTDR+1)
16 (UARTDR+1)
15 (UARTDR+1)
17 (UARTDR+1)
Generated baud rate
fcgck
fcgck
fcgck
fcgck
fcgck
TMP89FS60
[baud]
[baud]
[baud]
[baud]
[baud]