TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 332

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

21.1
Flash Memory Control
RA006
21.1
Flash memory control register 1
Flash memory control register 2
(0x0FD0)
(0x0FD1)
FLSCR1
FLSCR2
(FLSCR2), and flash memory standby control register (FLSSTB).
Note 1: It is prohibited to make a setting in "Reserved".
Note 2: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register.
Note 3: FLSMD must be set to either "0y010" or "0y101".
The flash memory is controlled by the flash memory control register 1 (FLSCR1), flash memory control register 2
Note 1: If "0xD5" is set on FLSCR2<CR1EN> with FLSCR1<FLSMD> set to "101", the flash memory goes into an active state,
Flash Memory Control
Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This means
that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift register
can be checked by reading the register FLSCRM.
Read/Write
FLSMD
BAREA
FAREA
Read/Write
CR1EN
Bit Symbol
Bit Symbol
After reset
After reset
and MCU consumes the same amount of current as it does during a read.
Flash memory command
sequence and toggle control
BOOTROM mapping control
Flash memory area select control
FLSCR1 register
enable/disable control
7
0
7
*
FLSMD
R/W
6
1
6
*
5
0
5
Others
Page 316
*
Others:
0xD5
010:
101:
00:
01:
10:
11:
0:
1:
Enable a change in the FLSCR1 setting
Reserved
Disable command sequence and toggle execution
Enable command sequence and toggle execution
Reserved
Hide BOOTROM
Show BOOTROM
Assign the data area 0x8000 through 0xFFFF
to the data area 0x8000 through 0xFFFF (standard mapping).
Assign the data area 0x1000 through 0x7FFF
to the data area 0x9000 through 0xFFFF.
Assign the code area 0x8000 through 0xFFFF
to the data area 0x8000 through 0xFFFF.
Assign the code area 0x1000 through 0x7FFF
to the data area 0x9000 through 0xFFFF.
BAREA
R/W
4
0
4
*
CR1EN
MCU mode
W
3
0
3
*
FAREA
R/W
2
0
2
*
-
Show BOOTROM
Serial PROM mode
R/W
1
0
1
-
*
TMP89FS60
R/W
0
0
0
*
-