TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 285

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA001
17.6
SCLK cycle time
SCLK "L" pulse width
SCLK "H" pulse width
SI input setup time
SI input hold time
SO output delay time
SCLK cycle time
SCLK "L" pulse width
SCLK "H" pulse width
SI input setup time
SI input hold time
SO output delay time
SCLK low-level input voltage
SCLK high-level input voltage
SCLK0 pin
SO0 pin
SI0 pin
AC Characteristics
Parameter
A6
C6
SCLK pin
SI pin
SO pin
Figure 17-18 Interval time between bytes
Symbol
t
t
A7
C7
t
t
t
t
SCLKH
SCLKL
t
t
t
SCYL
SCYH
t
SCYL
SCYH
t
t
SOD
t
t
SOD
SCY
SCY
SIS
SIH
SIS
SIH
Figure 17-17 AC Characteristics
B0
D0
V
Internal clock operation
SO pin and SCLK pin load capacity=100 pF
External clock operation
SO pin and SCLK pin load capacity=100 pF
SCLKL
t
B1
D1
SOD
t
SCYL
Page 269
B2
D2
Condition
t
SIS
t
SCY
V
t
SCLKH
SIH
Trailing edge at the
8th bit (receive edge)
t
SCYH
Symbol
tBI
Interval time between bytes
(V
tBI
V
SS
2 / fcgck
1 / fcgck
1 / fcgck
2 / fcgck
1 / fcgck
1 / fcgck
DD
= 0 V, V
− 25
− 15
−50
Min
60
35
50
50
0
0
× 0.70
Name
Leading edge at the
1st bit (transmit edge)
DD
= 4.5 V - 5.5 V, Topr = -40 to 85°C)
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Minimum time
V
4/fcgck
DD
TMP89FS60
Max
V
50
60
× 0.30
-
-
-
-
-
-
-
-
-
-
DD
Unit
ns
V