TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 294

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

18.4
Functions
RA002
18.4
18.4.1
18.4.2
18.4.3
18.4.3.1
Functions
bus interface is not being used.
Note that this makes the serial bus interface unusable. Setting POFFCR1<SBI0EN> to "1" enables the basic clock
supply to the serial bus interface and makes external interrupts usable.
using the serial bus interface for the first time, be sure to set POFFCR1<SBI0EN> to "1" in the initial setting of
the program (before the serial bus interface control registers are operated).
interface may operate unexpectedly.
tection in the slave mode.
detection.
tections. The slave addresses and "GENERAL CALL" sent from the master are ignored. No acknowledgement
is returned and no interrupt request is generated.
request is generated.
receiver mode. The slave device counts the clocks for an acknowledge signal and outputs an acknowledge signal
in the receiver mode.
the clocks for an acknowledge signal.
ment or non-acknowledgment mode
The serial bus interface has a low power consumption register (POFFCR1) that saves power when the serial
Setting POFFCR1<SBI0EN> to "0" disables the basic clock supply to the serial bus interface to save power.
After reset, POFFCR1<SBI0EN> is initialized to "0", and this makes the serial bus interface unusable. When
Do not change POFFCR1<SBI0EN> to "0" during the serial bus interface operation, otherwise serial bus
SBI0CR1<NOACK> enables and disables the slave address match detection and the GENERAL CALL de-
Clearing SBI0CR1<NOACK> to "0" enables the slave address match detection and the GENERAL CALL
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL de-
In the master mode, SBI0CR1<NOACK> is ignored and has no influence on the operation.
1-word data transfer consists of data and an acknowledge signal. When the data transfer is finished, an interrupt
SBI0CR1<BC> is used to select the number of bits of data to be transmitted/received subsequently.
The acknowledgment mode is activated by setting SBI0CR1<ACK> to "1".
The master device generates the clocks for an acknowledge signal and outputs an acknowledge signal in the
The non-acknowledgment mode is activated by setting SBI0CR1<ACK> to "0".
The master device does not generate the clocks for an acknowledge signal. The slave device does not count
Low Power Consumption Function
Selecting the slave address match detection and the GENERAL CALL detection
Selecting the number of clocks for data transfer and selecting the acknowledge-
Note:If SBI0CR1<NOACK> is cleared to "0" during data transfer in the slave mode, it remains at "1" and returns
The number of clocks for data transfer is set by using SBI0CR1<BC> and SBI0CR1<ACK>.
The acknowledgment mode is activated by setting SBI0CR1<ACK> to "1".
Number of clocks for data transfer
an acknowledge signal of data transfer.
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TMP89FS60