TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 182

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

13.4
Timer Function
RB002
13.4.6
13.4.6.1
13.4.6.2
In the PPG output mode, an arbitrary duty pulse is output by two timer registers.
Programmable pulse generate (PPG) mode
the source clock at TA0MOD<TA0CK>. Select continuous or one-shot PPG output at TA0CR<TA0MPPG>.
sure to set register values so that TA0DRA is larger than TA0DRB.
settings.
to "1" selects the "H" level as the initial state of the PPGA0 pin. Setting TA0CR<TA0TFF> to "0" selects the
"L" level as the initial state of the PPGA0 pin.
and TA0CR<TA0OVE, TA0TFF> is disabled. Be sure to complete the required mode settings before starting
the timer.
the PPGA0 pin is changed to the "H" level if TA0CR<TA0TFF> is "0", or the PPGA0 pin is changed to the
"L" level if TA0CR<TA0TFF> is "1".
set to timer register A (TA0DRA) is detected, the PPGA0 pin is changed to the "L" level if
TA0CR<TA0TEFF> is "0", or the PPGA0 pin is changed to the "H" level if TA0CR<TA0TFF> is "1". At
this time, an INTTCA0 interrupt request occurs. If the PPG output control TA0CR<TA0MPPG> is set to
"1" (one-shot), TA0CR<TA0S> is automatically cleared to "0" and the timer stops.
counting and PPG output. When TA0CR<TA0S> is set to "0" (including the auto stop by the one-shot oper-
ation) during the PPG output, the PPGA0 pin returns to the level set in TA0CR<TA0TFF>.
"0" during the operation cancels the one-shot operation and enables the continuous operation. Changing
TA0CR<TA0MPPG> from "0" to "1" during the operation clears TA0CR<TA0S> to "0" and stops the timer
automatically after the current pulse output is completed.
double buffer. When the values set to TA0DRA and TA0DRB are changed during the PPG output with the
double buffer enabled, the writing to TA0DRA and TA0DRB will not immediately become effective but will
become effective when a match between TA0DRA and the up counter is detected. If the double buffer is
disabled, the writing to TA0DRA and TA0DRB will become effective immediately. If the written value is
smaller than the up counter value, the up counter overflows. After a cycle, the counter match process is
executed to reverse the output.
Setting the operation mode selection TA0MOD<TA0M> to "011" activates the PPG output mode. Select
Set the PPG output cycle at TA0DRA and set the time until the output is reversed first at TA0DRB. Be
Note that this mode uses the PPGA0 pin. the PPGA0 pin must be set to the output mode beforehand in port
Set the initial state of the PPGA0 pin at the timer flip-flop TA0CR<TA0TFF>. Setting TA0CR<TA0TFF>
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to TA0MOD
after the timer is started, the up counter increments .
When a match between the up counter value and the value set to timer register B (TA0DRB) is detected,
Subsequently, the up counter continues counting. When a match between the up counter value and the value
If TA0CR<TA0MPPG> is set to "0" (continuous), the up counter is cleared to "0x0000" and continues
TA0CR<TA0MPPG> can be changed during the operation. Changing TA0CR<TA0MPPG> from "1" to
Timer registers A and B can be set to the double buffer. Setting TA0CR<TA0DBF> to "1" enables the
Setting
Operation
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TMP89FS60