TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 52

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
Quarter of the low-frequency clock
Figure 2-13 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck)
VINTWUC:
SYSCR2<SYSCK>
Gear clock (fcgck)
Main system clock
Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the high-frequency clock oscillation
(2)
up counter that the oscillation of the basic clock for the high-frequency clock has stabilized, and then
clear SYSCR2<SYSCK> to "0".
main system clock (fm) is switched to fcgck.
off the low-frequency clock oscillator.
voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is completed,
the NORMAL1 mode becomes active.
Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the NORMAL1
Note 2: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clearing
Note 3: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock
Note 4: When P0FC0 is "0", setting SYSCR2<XEN> to "1" causes a system clock reset.
Note 5: When SYSCR2<XEN> is set at "1", writing "1" to SYSCR2<XEN> does not cause the warm-up
Set SYSCR2<XEN> to "1" to enable the high-frequency clock (fc) to oscillate. Confirm at the warm-
When a maximum of 8/fs + 2.5/fcgck [s] has elapsed since SYSCR2<SYSCK> is cleared to "0", the
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XTEN> to "0" to turn
The SLOW mode is also released by a reset by the RESET pin, a power-on reset and a reset by the
(fs/4)
Switching from the SLOW1 mode to the NORMAL1 mode
DW
; #### Initialize routine ####
SET
¦
¦
LD
LD
circuit is confirmed at the warm-up counter (fc = 8 MHz, warm-up time = 4.0 ms)
mode.
SYSCR2<XTEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization, fm is
stopped for a period of 2.5/fcgck [s] or shorter.
counter to start counting the source clock.
PINTWUC
(P0FC).2
(WUCCR), 0x09
(WUCDR), 0x7D
When the rising edge of fs/4 is
detected twice after SYSCR2<SYSCK>
is changed from 1 to 0, f is stopped
for synchronization.
Page 36
;INTWUC vector table
;P0FC2 = 1 (Uses P02/03 as oscillators)
;WUCCR<WUCDIV> = 10 (Divided by 2)
;WUCCR<WUCSEL> = 0 (Selects fc as the source clock)
;Sets the warm-up time
;(Determine the time depending on the frequency and the oscillator
;characteristics)
;4ms / 32us = 125 → 0x7D
2.5/fcgck(max.)
When the rising edge of fcgck is detected
twice after fm is stopped, fm is switched to fcgck.
TMP89FS60