TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 240

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

16.4
Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed
RA001
16.4
settings (for example, stop bit and parity) are not changed accidentally during the UART operation.
write instruction is executed on the register when it is protected from being changed, the bits remain unchanged and
keep their previous values.
Changed
Table 16-3 Changing of UART0CR1 and UART0CR2
The TMP89FS60 has a function that protects the registers from being changed so that the UART communication
Specific bits of UART0CR1 and UART0CR2 can be changed only under the conditions shown in Table 16-3. If a
Protection to Prevent UART0CR1 and UART0CR2 Registers from Being
UART0CR1<IRDASEL>
UART0CR2<STOPBR>
UART0CR1<STOPBT>
UART0CR2<RXDNC>
UART0CR2<RTSEL>
UART0CR1<EVEN>
UART0CR1<BRG>
Bit to be changed
UART0CR1<PE>
Transfer base clock selection
Selection of number of RT
Selection of RXD pin input
TXD pin output selection
Transmit stop bit length
Receive stop bit length
noise rejection time
Parity selection
Parity addition
Function
clocks
Page 224
UART0CR1
<TXE>
Both of these bits are "0"
Both of these bits are "0"
-
Conditions that allow the bit to be changed
UART0SR
<TBSY>
All of these bits are "0"
All of these bits are "0"
-
UART0CR1
<RXE>
Both of these bits are "0"
-
-
UART0SR
<RBSY>
TMP89FS60
-
-