TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 200

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

14.4
Functions
RA005
14.4.2
14.4.2.1
14.4.2.2
14.4.2.3
pin. The operation of TC00 is described below, and the same applies to the operation of TC01.
In the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 or TC01
8-bit event counter mode
"0" and T00MOD<EIN0> to "1". Set the count value to be used for the match detection as an 8-bit value at
the timer register T00REG.
becomes invalid. Be sure to complete the required mode settings before starting the timer.
pin. When a match between the up-counter value and the T00REG set value is detected, an INTTC00 interrupt
request is generated and the up counter is cleared to "0x00". After being cleared, the up counter restarts
counting. Setting T001CR<T00RUN> to "0" during the timer operation makes the up counter stop counting
and be cleared to "0x00".
(in SLOW1/2 or SLEEP1 mode), and a pulse width of two machine cycles or more is required at both the "H"
and "L" levels.
(Example) Operate TC00 in the 8-bit event counter mode and generate an interrupt each time 16 falling edges are detected
TC00 is put into the 8-bit event counter mode by setting T00MOD<TCM0> to "00", T001CR<TCAS> to
Set T00MOD<DBE0> to "1" to use the double buffer.
Setting T001CR<T00RUN> to "1" starts the operation. After the timer is started, writing to T00MOD
Setting T001CR<T00RUN> to "1" allows the 8-bit up counter to increment at the falling edge of the TC00
The maximum frequency to be supplied is fcgck/2
Refer to "14.4.1.3 Double buffer".
Setting
Operation
Double buffer
at the TC00 pin.
LD
DI
SET
EI
LD
LD
SET
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xC4
(T00REG),0x10
(T001CR).0
Page 184
2
[Hz] (in NORMAL1/2 or IDLE1/2 mode) or fs/24 [Hz]
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects to the 8-bit event counter mode
; Sets the timer register
; Starts TC00
TMP89FS60