TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 13

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

19. Key-on Wakeup (KWU)
20. 10-bit AD Converter (ADC)
18.2 Configuration.......................................................................................................................274
18.3 Control.................................................................................................................................275
18.4 Functions..............................................................................................................................278
18.5 Data Transfer of I2C Bus.....................................................................................................288
18.6 AC Specifications................................................................................................................295
18.7 Revision History..................................................................................................................297
19.1 Configuration.......................................................................................................................299
19.2 Control.................................................................................................................................300
19.3 Functions..............................................................................................................................301
20.1 Configuration.......................................................................................................................303
20.2 Control.................................................................................................................................304
20.3
20.4
20.5 Starting STOP/IDLE0/SLOW Modes.................................................................................310
20.6 Analog Input Voltage and AD Conversion Result..............................................................311
20.7 Precautions about the AD Converter...................................................................................312
20.8 Revision History..................................................................................................................313
18.1.2
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
20.3.1
20.3.2
20.3.3
20.7.1
20.7.2
20.7.3
18.4.3.1
18.4.3.2
18.4.4.1
18.4.4.2
18.5.3.1
18.5.3.2
Functions.............................................................................................................................308
Register Setting...................................................................................................................310
Free data format.............................................................................................................................................................273
Low Power Consumption Function...............................................................................................................................278
Selecting the slave address match detection and the GENERAL CALL detection.......................................................278
Selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode......
Serial clock....................................................................................................................................................................280
Master/slave selection....................................................................................................................................................282
Transmitter/receiver selection........................................................................................................................................282
Start/stop condition generation......................................................................................................................................282
Interrupt service request and release..............................................................................................................................283
Setting of serial bus interface mode...............................................................................................................................284
Device initialization.......................................................................................................................................................288
Start condition and slave address generation.................................................................................................................288
1-word data transfer.......................................................................................................................................................289
Stop condition generation..............................................................................................................................................292
Restart............................................................................................................................................................................293
Single mode...................................................................................................................................................................308
Repeat mode..................................................................................................................................................................308
AD operation disable and forced stop of AD operation................................................................................................309
Analog input pin voltage range......................................................................................................................................312
Analog input pins used as input/output ports.................................................................................................................312
Noise countermeasure....................................................................................................................................................312
278
Software reset..............................................................................................................................................................284
Arbitration lost detection monitor................................................................................................................................284
Slave address match detection monitor.......................................................................................................................286
GENERAL CALL detection monitor..........................................................................................................................286
Last received bit monitor.............................................................................................................................................287
Slave address and address recognition mode specification.........................................................................................287
Number of clocks for data transfer
Output of an acknowledge signal
Clock source
Clock synchronization
When SBI0SR2<MST> is "1" (Master mode)
When SBI0SR2<MST> is "0" (Slave mode)
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