TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 175

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RB002
13.4.3
13.4.3.1
13.4.3.2
13.4.3.3
13.4.3.4
In the event counter mode, the up counter counts up at the edge of the input to the TCA0 pin.
Event counter mode
TA0MOD<TA0TED> to "0" selects the rising edge, and setting it to "1" selects the falling edge for counting
up.
in port settings.
and TA0CR<TA0OVE> is disabled. Be sure to complete the required mode settings before starting the timer.
counter increments.
an INTTCA0 interrupt request is generated and the up counter is cleared to "0x0000". After being cleared,
the up counter continues counting and counts up at each edge of the input to the TCA0 pin. Setting
TA0CR<TA0S> to "0" during the operation causes the up counter to stop counting and be cleared to "0x0000".
[Hz] (in the SLOW 1/2 or SLEEP 1 mode), and a pulse width of two machine cycles or more is required at
both the "H" and "L" levels.
Setting the operation mode selection TA0MOD<TA0M> to "010" activates the event counter mode.
Set the trigger edge at the external trigger input selection TA0MOD<TA0TED>. Setting
Note that this mode uses the TA0 input pin, and the TCA0 pin must be set to the input mode beforehand
The operation is started by setting TA0CR<TA0S> to "1". After the timer is started, writing to TA0MOD
After the event counter mode is started, when the selected trigger edge is input to the TCA0 pin, the up
When a match between the up counter value and the value set to timer register A (TA0DRA) is detected,
The maximum frequency to be supplied is fcgck/2 [Hz] (in the NORMAL 1/2 or IDLE 1/2 mode) or fs/2
Refer to "13.4.1.3 Auto capture".
Refer to "13.4.1.4 Register buffer configuration".
Setting
Operation
Auto capture
Register buffer configuration
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TMP89FS60