TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 295

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA002
Figure 18-5 Number of Clocks for Data Transfer and SBI0CR1<BC> and SBI0CR1<ACK>
18.4.3.2
bits, generates the clocks for an acknowledge signal, and generates an interrupt request.
signal, and generates an interrupt request.
of data bits, and generates an interrupt request.
is shown in Table 18-1.
keeps the set value.
acknowledge signal.
INTSBI0 interrupt request
Table 18-1 Relationship between the Number of Clocks for Data Transfer and SBI0CR1<BC> and
In the acknowledgment mode, the master device generates the clocks that correspond to the number of data
The slave device counts the clocks that correspond to the data bits, counts the clocks for an acknowledge
The non-acknowledgment mode is activated by setting SBI0CR1<ACK> to "0".
In the non-acknowledgment mode, the master device generates the clocks that correspond to the number
The slave device counts the clocks that correspond to the data bits, and generates an interrupt request.
The relationship between the number of clocks for data transfer and SBI0CR1<BC> and SBI0CR1<ACK>
BC is cleared to "000" by the start condition.
Therefore, the slave address and the direction bit are always transferred in 8-bit units. In other cases, BC
In the acknowledgment mode, the SDA0 pin changes as follows during the period of the clocks for an
Note:SBI0CR1<ACK> must be set before transmitting or receiving a slave address. When SBI0CR1<ACK>
Output of an acknowledge signal
000
001
010
011
100
101
110
111
BC
・ In the master mode
is cleared, the slave address match detection and the direction bit detection are not executed properly.
SBI0CR1<ACK>
1
Number of clocks for data
ACK=0 (Non-acknowledgment mode)
transfer
2
SBI0CR1<BC>="110",
SBI0CR1<ACK>="0"
8
1
2
3
4
5
6
7
3
4
Number of data bits
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5
8
1
2
3
4
5
6
7
6
Number of clocks for data
ACK=1 (Acknowledgment mode)
transfer
1
SBI0CR1<BC>="011",
SBI0CR1<ACK>="1"
9
2
3
4
5
6
7
8
2
Number of data bits
3
8
1
2
3
4
5
6
7
4
TMP89FS60