TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 32

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
System control register 2
Warm-up counter control register
(0x0FDD)
(0x0FCD)
SYSCR2
WUCCR
Note 3: If the STOP mode is activated with SYSCR1<OUTEN> set at "0", the port internal input is fixed to "0". Therefore, an
Note 4: The P11 pin is also used as the STOP pin. When the STOP mode is activated, the pin reverts to high impedance state
Note 5: Writing of the second byte data will be executed improperly if the operation is switched to the STOP state by an instruction,
Note 6: Don't set SYSCK1<DV9CK> to "1" before the oscillation of the low-frequency clock oscillation circuit becomes stable.
Note 7: In the SLOW1/2 or SLEEP1 mode, fs/4 is input to stage 9 of the divider, regardless of the state of SYSCR1< DV9CK >.
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]
Note 2: WDT: Watchdog timer, TG: Timing generator
Note 3: Don't set both SYSCR2<IDLE> and SYSCR2<TGHALT> to "1" simultaneously.
Note 4: Writing of the second byte data will be executed improperly if the operation is switched to the IDLE state by an instruction,
Note 5: When the IDLE1/2 or SLEEP1 mode is released, SYSCR2<IDLE> is cleared to "0" automatically.
Note 6: When the IDLE0 or SLEEP0 mode is released, SYSCR2<TGHALT> is cleared to "0" automatically.
Note 7: Bits 7, 1 and 0 of SYSCR2 are read as "0".
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: WUCCR<WUCRST> is cleared to "0" automatically, and need not be cleared to "0" after being set to "1".
Note 3: Bits 7 to 4 of WUCCR are read as "0". Bit 0 is read as "1".
WUCRST
WUCSEL
WUCDIV
TGHALT
Read/Write
SYSCK
Read/Write
Bit Symbol
Bit Symbol
external interrupt may be set at the falling edge, depending on the pin state when the STOP mode is activated.
and is put in input mode, regardless of the state of SYSCR1<OUTEN>.
such as LDW, which executes 2-byte data transfer at a time.
After reset
such as LDW, which executes 2-byte data transfer at a time.
After reset
XTEN
IDLE
XEN
Controls the high-frequency clock
oscillation circuit
Controls the low-frequency clock os-
cillation circuit
Selects a system clock
CPU and WDT control
(IDLE1/2 or SLEEP1 mode)
TG control
(IDLE0 or SLEEP0 mode)
Resets and stops the warm-up coun-
ter
Selects the frequency division of the
warm-up counter source clock
Selects the warm-up counter source
clock
WUCRST
W
R
7
0
7
0
-
XEN
R/W
R
6
1
6
0
-
XTEN
R/W
R
5
0
5
0
00 :
01 :
10 :
11 :
-
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0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
0 :
1 :
Stop oscillation
Continue or start oscillation
Stop oscillation
Continue or start oscillation
Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode)
Low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode)
Operate the CPU and the WDT
Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode)
Enable the clock supply from the TG to all the peripheral circuits
Disable the clock supply from the TG to the peripheral circuits except the
TBT (Activate IDLE0 or SLEEP0 mode)
-
Clear and stop the counter
Source clock
Source clock / 2
Source clock / 2
Source clock / 2
Select the high-frequency clock (fc)
Select the low-frequency clock (fs)
SYSCK
R/W
R
4
0
4
0
-
2
3
IDLE
R/W
3
0
3
1
WUCDIV
R/W
TGHALT
R/W
2
0
2
1
WUCSEL
R/W
R
1
0
1
0
-
TMP89FS60
R
0
0
0
R
1
-
-