TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 34

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.3
System clock controller
RB000
2.3.3.2
(a) Crystal or ceramic
XIN
oscillator
clock oscillation circuit and switching the pin function to ports are controlled by the software and hardware.
register P0FC.
is switched to the STOP mode as described in "2.3.5 Operation mode control circuit".
lation, an internal factor reset is generated depending on the combination of values of the clock selected as
the main system clock, SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function control register P0FC0.
(fc) and inputs it to the timing generator.
changed.
Table 2-1 Prohibited Combinations of Oscillation Enable Register Conditions
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Enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency
The software control is executed by SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function control
The hardware control is executed by reset release and the operation mode control circuit when the operation
To prevent the dead lock of the CPU core due to the software-controlled enabling/disabling of the oscil-
The clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency clock
Selects a divided clock at CGCR<FCGCKSEL>.
Two machine cycles are needed after CGCR<FCGCKSEL> is changed before the gear clock (fcgck) is
Clock gear
Note:No hardware function is available for external direct monitoring of the basic clock. The oscillation fre-
Note:It takes a certain period of time after SYSCR2<SYSCK> is changed before the main system clock is
P0FC0
0
High-frequency clock
XOUT
quency can be adjusted by programming the system to output pulses at a certain frequency to a port
(for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring
the output. An adjustment program must be created in advance for a system that requires adjustment
of the oscillation frequency.
switched. If the currently operating oscillation circuit is stopped before the main system clock is switch-
ed, the internal condition becomes as shown in Table 2-1 and a system clock reset occurs. For details
of clock switching, refer to "2.3.6 Operation Mode Control".
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SYSCR2
<XEN>
0
0
1
Figure 2-4 Examples of Oscillator Connection
(b) External oscillator
XIN
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SYSCR2
<XTEN>
0
0
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<SYSCK>
SYSCR2
XOUT
(Open)
1
0
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All the oscillation circuits are stopped.
The low-frequency clock (fs) is selected as the main system
clock, but the low-frequency clock oscillation circuit is stop-
ped.
The high-frequency clock (fc) is selected as the main system
clock, but the high-frequency clock oscillation circuit is stop-
ped.
The high-frequency clock oscillation circuit is allowed to os-
cillate, but the port is set as a general-purpose port.
(c) Crystal oscillator
XTIN
State
XTOUT
Low-frequency clock
(d) External oscillator
XTIN
TMP89FS60
XTOUT
(Open)