TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 115

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TMP89xy60UG/FG

Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP89xy60UG/FG

Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
RA007
Port P0 output latch
Port P0 input/output control
Port P0 function control
Port P0 built-in pull-up resistor control
(0x0F1A)
(0x0F34)
(0x0F27)
(0x0000)
P0DR
P0CR
P0FC
P0PU
Note:P0CR1 and P0CR0 must be clear to "0".
Note 1: When SYSCR2<XEN> is "1", setting P0FC0 to "0" generates a system clock (internal factor) reset. Normally, ports P00
Note 2: Symbol "I" means secondary function input
Function
Function
Function
Function
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
or P01 are not used as ports, so P0FC0 must be set to "1".
After reset
0:
1:
0:
1:
0:
1:
0:
1:
R
R
R
R
7
0
7
0
7
0
7
0
-
-
-
-
R
R
R
R
6
0
6
0
6
0
6
0
-
-
-
-
R
R
R
R
5
0
5
0
5
0
5
0
-
-
-
-
Page 99
R
R
R
R
4
0
4
0
4
0
4
0
-
-
-
-
Outputs L level when the output mode is selected.
Outputs H level when the output mode is selected.
Input mode (port input)
Output mode (port output)
The built-in pull-up resistor is not connected.
The built-in pull-up resistor is connected. (The resistor is
connected in the input mode only. Under any other con-
ditions, setting to "1" does not make the resistor connec-
ted.)
P0CR3
P0PU2
R/W
R/W
R/W
P03
R
0
3
0
3
0
3
3
0
-
Port func-
tion
XTIN (I)
P0CR2
P0PU2
P0FC2
R/W
R/W
R/W
R/W
P02
2
0
2
0
2
0
2
0
P0CR1
P0PU1
R/W
R/W
R/W
P01
R
1
0
1
0
1
0
1
0
-
TMP89FS60
Port func-
tion
P0CR0
P0PU0
P0FC0
XIN (I)
R/W
R/W
R/W
R/W
P00
0
0
0
0
0
1
0
0

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