TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 95
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMP89xy60UG/FG
Manufacturer Part Number
TMP89xy60UG/FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP89XY60UGFG.pdf
(432 pages)
Specifications of TMP89xy60UG/FG
Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
M/F
Rom Size
32/60
Ram Size
3K
Driver Led
8
Driver Lcd
-
Spi/sio Channels
-
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
Y
Number Of I/o Ports
58
Power Supply (v)
4.3 to 5.5
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RA000
8-bit up counter value
When WDCTR<WDTW> is “10”
Writing of 4EH (clear code)
Reading of WDST
Watchdog timer interrupt
request signal
WDST<WINTST1>
WDST<WINTST2>
for releasing the 8-bit up counter outside the clear time.
WDST<WINTST2> and WDST<WINTST1> in the watchdog timer interrupt service routine.
same time as the condition for turning WDST<WINTST2> or WDST<WINTST1> to "1" is satisfied,
WDST<WINTST2> or WDST<WINTST1> is set to "1", rather than being cleared.
WDST<WINTST1> is set to "1" when a watchdog timer interrupt request signal occurs due to the operation
You can know which factor has caused a watchdog timer interrupt request signal by reading
WDST<WINTST2> and WDST<WINTST1> are cleared to "0" when WDST is read. If WDST is read at the
0xFF 0x00 0x01
Figure 5-4 Changes in the Watchdog Timer Status
Interrupt request signal generated by clearing
the 8-bit up counter outside the clear time
Outside the clear time
0x3F
0x40
Page 79
0x7F 0x80
0xBF 0xC0
Clear time
0xFF 0x00
Interrupt request signal generated by the
overflow of the 8-bit up counter
0x01
TMP89FS60
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