TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 158

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

12.1
Time Base Timer
RA001
12.1.3
Note 4: When SYSCR1<DV9CK> is "1" in the NORMAL 1/2 or IDLE1/2 mode, the interrupt request is subject to some fluctuations
Note 5: Bits 7 to 4 of TBTCR are read as "0".
be changed when TBTCR<TBTEN> is "0". Otherwise, the INTTBT interrupt request is generated at unexpected
timing.
clock. When TBTCR<TBTEN> is cleared to "0", no interrupt request signal will occur.
interrupt request is enabled. Therefore, the period from when the time TBTCR<TBTEN> is set to "1" to the time
when the first interrupt request occurs is shorter than the frequency period set at TBTCR<TBTCK>.
mode, The interrupt request will not occur at the expected timing due to synchronization of the gear clock (fcgck)
and the low-frequency clock (fs). It is recommened that the operation mode is changed when TBTCR<TBTEN>
is "0".
Table 12-1 Time Base Timer Interrupt Frequency (Example: when fcgck = 8.0 MHz and fs = 32.768
Select the source clock frequency for the time base timer by TBTCR<TBTCK>. TBTCR<TBTCK> should
Setting TBTCR<TBTEN> to "1" causes interrupt request signals to occur at the falling edge of the source
When the operation is changed to the STOP mode, TBTCR<TBTEN> is cleared to "0".
The source clock of the time base timer operates regardless of the TBTCR<TBTEN> value.
A time base timer interrupt is generated at the first falling edge of the source clock after a time base timer
When the operation is changed from NORMAL mode to SLOW mode or from SLOW mode to NORMAL
Functions
to synchronize fs and fcgck.
TBTCK
000
001
010
011
100
101
110
111
TBTCR<TBTEN>
INTTBT interrupt
request
kHz)
Source clock
NORMAL1/2, IDLE1/2 mode
Figure 12-2 Time Base Timer Interrupt
DV9CK = 0
1953.13
3906.25
244.14
976.56
7812.5
31250
1.91
7.63
Time base timer enable
Time base timer interrupt frequency [Hz]
Page 142
NORMAL1/2, IDLE1/2 mode
Interrupt period
DV9CK = 1
Reserved
1024
2048
4096
128
512
1
4
SLOW1/2, SLEEP1 mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
4
TMP89FS60