TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 216

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

14.4
Functions
RA005
T001CR<T01RUN>
TC00 pin input
Counter
Write to T00REG
Write to T01REG
T01+00REG
INTTC00 interrupt
request
T001CR<T01RUN>
TC00 pin input
Counter
Write to T00REG
Write to T01REG
Double buffer
T01+00REG
INTTC00 interrupt
request
(Example) Operate TC00 and TC01 in the 16-bit event counter mode and generate an interrupt each time the 384th falling
Figure 14-12 16-bit Event Counter Mode Timing Chart
edge is detected at the TC00 pin
Write m
Write m
LD
DI
SET
EI
LD
LD
LD
LD
Write k
Write k
km
km
km
Reflected by writing to T01REG
Reflected by writing to T01REG
0
0
Timer start
Timer start
1
1
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xC4
(T00REG),0x80
(T01REG),0x10
(T001CR),0x06
2
2
When the double buffer is disabled (T01MOD<DBE1>=”0”)
When the double buffer is enabled (T01MOD<DBE1>=”1”)
3
3
Match detection
Match detection
4
4
Page 200
km-1
km-1
km
km
0
0
Counter
clear
Counter
clear
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 16-bit event counter mode
; Sets the timer register
; Sets the timer register
; Starts TC00 and TC001 (16-bit mode)
1
1
2
2
Write s
Write s
3
3
Write r
Match detection
Write r
rs
rs
Reflected by writing to T01REG
Reflected by writing to T01REG
km-1
rs-1
km
rs
Counter
clear
Reflected by
an interrupt
rs
0
Counter
clear
0
1
1
2
Timer stop
Counter
clear
rs-1
0
TMP89FS60
rs
Counter
clear
0
1