TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 54

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.4
Reset Control Circuit
RB000
2.4
2.4.1
2.4.2
System control register 3
(0x0FDE)
SYSCR3
P10(RESET)
Power-on reset signal
Voltage detection reset 1 signal
Voltage detection reset 2 signal
Watchdog timer reset signal
System clock reset signal
Trimming data reset signal
Flash standby reset signal
Reset Control Circuit
The reset circuit controls the external and internal factor resets and initializes the system.
Note 1: The enabled SYSCR3<RSTDIS> is initialized by a power-on reset only, and cannot be initialized by an external reset
Note 2: The value of SYSCR3<RSTDIS> is invalid until 0xB2 is written into SYSCR4.
(SYSCR4), system control status register (SYSSR4) and the internal factor reset detection status register
(IRSTSR).
Configuration
Control
The reset control circuit consists of the following reset signal generation circuits:
The reset control circuit is controlled by system control register 3 (SYSCR3), system control register 4
RSTDIS
Read/Write
Bit Symbol
1. External reset input (external factor)
2. Power-on reset (internal factor)
3. Voltage detection reset 1 (internal factor)
4. Voltage detection reset 2 (internal factor)
5. Watchdog timer reset (internal factor)
6. System clock reset (internal factor)
7. Trimming data reset (internal factor)
8. Flash standby reset (internal factor)
After reset
input or internal factor reset. The value written in SYSCR3 is reset by a power-on reset, external reset input or internal
factor reset.
P10 port
External reset input enable register
R
7
0
-
Figure 2-14 Reset Control Circuit
R
6
0
-
R
5
0
-
Page 38
Warm-up
counter reset
signal
0 :
1 :
Enables the external reset input.
Disables the external reset input.
R
4
0
-
Internal factor reset detection status register,
Voltage detection circuit reset signal
External reset input enable reset signal
System clock control circuit
Warm-up counter
R
3
0
-
(RVCTR)
R/W
2
0
(RAREA)
R/W
1
0
CPU/peripheral
circuits reset signal
TMP89FS60
RSTDIS
R/W
0
0