TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 322

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

20.2
Control
RA002
AD converter control register 2
ADCCR2
(0x0035)
Table 20-1 ACK Settings and Conversion Times Relative to Frequencies
Note 1: Spaces indicated by "-" in the above table mean that it is prohibited to establish conversion times in these spaces.
Note 2: Above conversion times do not include the time shown below.
Note 3: The conversion time must be longer than the following time by analog reference voltage (VAREF).
Note 1: Make sure that you make the ACK setting when AD conversion is in a halt condition (ADCCR2<ADBF>="0").
Note 2: Make sure that you write "0" to bit 3 of ADCCR2.
Note 3: If STOP, IDLE0 or SLOW mode is started, EOCF and ADBF are initialized to "0".
Note 4: If the AD converted value register (ADCDRH) is read, EOCF is cleared to "0". It is also cleared to "0" if AD conversion is
Note 5: If an instruction to read ADCCR2 is executed, 0 is read from bits 3 through 5.
ACK setting
000
001
010
011
100
101
11*
Read/Write
Bit Symbol
fcgck: High Frequency oscillation clock [Hz]
- Time from when ADCCR1<ADRS> is set to 1 to when AD conversion is started
- Time from when AD conversion is finished to when a converted value is stored in ADCDRL and ADCDRH.
If ACK = 00*, the longest conversion time is 10/fcgck (s). If ACK = 01*, it is 32/fcgck (s). If ACK = 10*, it is 128/fcgck(s).
- VAREF = 4.5 to 5.5 V
- VAREF = 2.7 to 5.5 V
- VAREF = 2.5 to 5.5 V
After reset
started (ADCCR1<ADRS>="1") without reading ADCDRH after completing AD conversion in single mode.
EOCF
ADBF
ACK
Conversion
1248/fcgck
156/fcgck
312/fcgck
624/fcgck
39/fcgck
78/fcgck
time
AD conversion end flag
AD conversion BUSY flag
AD conversion time select (exam-
ples of AD conversion time are
shown in the table below)
EOCF
156.0 μs
R
19.5 μs
39.0 μs
78.0 μs
7
0
8MHz
-
-
124.8 μs
15.6 μs
31.2 μs
62.4 μs
15.6 μs or longer
31.2 μs or longer
124.8 μs or longer
ADBF
5MHz
R
6
0
-
-
156.0 μs
19.5 μs
39.0 μs
78.0 μs
4MHz
-
-
5
R
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0
-
000:
001:
010:
011:
100:
101:
110:
111:
Reserved
0:
1:
0:
1:
124.8 μs
2.5MHz
15.6 μs
31.2 μs
62.4 μs
Frequency (fcgck)
Before conversion or during conversion
Conversion end
AD conversion being halted
AD conversion being executed
39/fcgck
78/fcgck
156/fcgck
312/fcgck
624/fcgck
1248/fcgck
Reserved
Reserved
-
-
R
4
0
-
156.0 μs
19.5 μs
39.0 μs
78.0 μs
2MHz
-
-
"0"
W
3
0
156.0 μs
39.0 μs
78.0 μs
1MHz
-
-
-
156.0 μs
0.5MHz
78.0 μs
2
0
-
-
-
-
0.25 MHz
156.0 μs
ACK
R/W
-
-
-
-
-
1
0
TMP89FS60
0
0