TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 292

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

18.3
Control
RA002
Serial bus interface control register 1
Serial bus interface control register 2
Serial bus interface status register 2
SBI0CR1
SBI0CR2
SBI0SR2
(0x0022)
(0x0023)
(0x0023)
Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock oscillation circuit clock
Note 2: Don't change the contents of the registers when the start condition is generated, the stop condition is generated or the
Note 3: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
Note 5: When fcgck is 4MHz, SCK should be not set to 0y000, 0y001 or 0y010 because it is not possible to satisfy the bus
Note 1: When SBI0CR2<SBIM> is "0", no value can be written to SBI0CR2 except SBI0CR2<SBIM>. Before writing values to
Note 2: Don't change the contents of the registers, except SBI0CR2<SWRST>, when the start condition is generated, the stop
Note 3: Make sure that the port is in a high state before switching the port mode to the serial bus interface mode. Make sure that
Note 4: SBI0CR2 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit oper-
Note 5: After a software reset is generated, all the bits of SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
Note 6: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
Note 1: * : Unstable
Note 2: When SBI0CR2<SBIM> becomes "0", SBI0SR is initialized.
Note 3: After a software reset is generated, all the bits of the SBI0CR2 register except SBI0CR2<SBIM> and the SBI0CR1, I2C0AR
Note 4: When the operation is switched to STOP, IDLE0 or SLOW mode, the SBI0CR2 register, except SBI0CR2<SBIM>, and
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
After reset
data transfer is in progress. Write data to the registers before the start condition is generated or during the period from
when an interrupt request is generated for stopping the data transfer until it is released.
and SBI0SR2 registers are initialized.
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
specification of fast mode.
After reset
SBI0CR2, write "1" to SBI0CR2<SBIM> to activate the serial bus interface mode.
condition is generated or the data transfer is in progress. Write data to the registers before the start condition is generated
or during the period from when an interrupt request is generated for stopping the data transfer until it is released.
the bus is free before switching the serial bus interface mode to the port mode.
ation.
and SBI0SR2 registers are initialized.
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
After reset
and SBI0SR2 registers are initialized.
the SBI0CR1, I2C0AR and SBI0DBR registers are initialized.
MST
MST
W
R
7
0
7
0
7
0
R/W
TRX
TRX
BC
W
R
6
0
6
0
6
0
BB
BB
W
R
5
0
5
0
5
0
Page 276
ACK
R/W
PIN
PIN
W
R
4
0
4
1
4
1
NOACK
SBIM
R/W
AL
W
R
3
0
3
0
3
0
AAS
R
R
2
0
2
0
2
0
-
SCK
R/W
AD0
R
1
0
1
1
0
TMP89FS60
SWRST
W
0
LRB
R
0
0
0
0
*