TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 68

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

3.3
Interrupt Enable Register (EIR)
RA003
Interrupt latch (ILL)
Interrupt latch (ILH)
Interrupt latch (ILE)
Interrupt latch (ILD)
(0x0FE0)
(0x0FE1)
(0x0FE2)
(0x0FE3)
ILH
ILD
ILL
ILE
Note 1: IL3 is a read-only register. Writing the register does not affect interrupt latch.
Note 2: In the main program, before manipulating an interrupt latch (IL), be sure to clear the interrupt master enable flag (IMF) to
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Note 4: When a read instruction is executed on ILL, bits 0 to 2 are read as "0". Other unused bits are read as "0".
IL27 to IL4
Read/Write
Read/Write
Read/Write
Read/Write
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
"0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI
instruction).
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if
using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1".
Function
Function
Function
Function
IL3
Interrupt latch
INTSBI0/IN-
INTTXD0
INTTXD1
TSIO0
IL15
IL23
R/W
R/W
R/W
IL7
R
7
0
7
0
7
0
7
0
-
INTRXD0 /
INTRXD1/
INTTCA0
INTSIO0
INTSIO1
R/W
IL14
R/W
IL22
R/W
IL6
R
6
0
6
0
6
0
6
0
-
INTTCA1
INTTC01
INTTBT
R/W
IL13
R/W
IL21
R/W
IL5
R
5
0
5
0
5
0
5
0
-
Page 52
0:
1:
0:
1:
No interrupt request
Interrupt request
No interrupt request
Interrupt request
INTTC00
INTWUC
INT4
R/W
IL12
R/W
IL20
R/W
IL4
R
4
0
4
0
4
0
4
0
-
Read
INTTXD2
INTWDT
INTRTC
INT3
IL11
R/W
IL19
R/W
IL27
R/W
IL3
R
3
0
3
0
3
0
3
0
INTRXD2
INTADC
INT2
IL10
R/W
IL18
R/W
IL26
R/W
R
2
0
2
0
2
0
2
0
-
Clears the interrupt request
(Notes 2 and 3)
Does not clear the interrupt re-
quest
(Interrupt is not set by writing "1".)
INTVLTD
INTTC03
INT1
R/W
IL17
R/W
IL25
R/W
IL9
R
1
0
1
0
1
0
1
0
-
Write
TMP89FS60
-
INTTC02
INT5
INT0
R/W
IL16
R/W
IL24
R/W
IL8
R
0
0
0
0
0
0
0
0
-