tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 195

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.1 Address and Data Pins
(1) Address and data pin settings
The TMP19A61 can be set to either separate bus or multiplexed bus mode. Setting the BUSMD pin
to the "L" level at a reset activates the separate bus mode, and setting the pin to the "H" level activates
the multiplexed bus mode. Table 8.1 shows relation among bus mode, address and data pins.
(2) Operation after reset
After reset, the control register (B23CS) of the block address area 2 (CS2) is automatically
Port
Port 0(P00~P07)
Port 1(P10~P15)
Port 2(P20~P27)
Port 5(P50~P57)
Port 6(P60~P67)
Port 3(P37)
After reset, set the block address area with the BMA2 register.
enabled and the following are set.
B23CS<B2E>
B23CS<B2W4:0>
B23CS<B2BUS1:0> = 01
B23CS<B2RCV1:0> = 10
B23CS<B2WCV1:0> = 10
B23CS<B2WCV1:0> = 000
Table 8.1 Bus Mode, Address and Data Pins
TMP19A61(rev1.0)-8-194
General purpose port
BUSMD = ”L”
A16~A23
Separate
D8~D15
A8~A15
D0~D7
A0~A7
= 1
= 00001 (1 WAIT insertion)
(CS2 enabled)
(16bit bus setting)
(2 cycles insertion for read recovery time)
(2 cycles insertion for write recovery time)
(0 cycle insertion for CS recovery time)
AD08~AD15/A8~A15
BUSMD = ”H”
AD0~AD07
A16~A24
Multiplex
ALE
−
−
TMP19A61