tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 428

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ADAREG19H
(0xFFFF_F803)
ADAREG08H
(0xFFFF_F801)
ADAREG08L
(0xFFFF_F800)
ADAREG19L
(0xFFFF_F802)
•
•
•
Converted channel X value
an A/D converted value is stored. A read of a lower register (ADAREGxL) will set this bit to "0."
Bit 1 of ADAREG08L/ADAREG19L is the over RUN flag <OVRx>. This bit is set to "1" if a conversion result is
overwritten before both conversion result storage registers (ADAREGxH,ADAREGxL) are read. A read of a flag will
clear this bit to "0."
Values read from bits 5 through 2 of ADAREG08L/ADAREG19L are always "1."
Bit 0 of ADAREG08L/ADAREG19L is the A/D conversion result storage flag <ADRxRF>. This bit is set to "1" after
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Function
Function
A/D conversion result.
A/D conversion result.
ADR01
Store lower 2 bits of
ADR09
ADR11
Store lower 2 bits of
ADR19
Fig. 16.4 Registers related to the A/D Converter
7
7
7
7
Lower A/D Conversion Result Register 08
Upper A/D Conversion Result Register 08
Lower A/D Conversion Result Register 19
Upper A/D Conversion Result Register 19
R
R
ADREGxH
0
0
9
TMP19A61 (rev1.0)16-427
ADR00
ADR08
ADR10
ADR18
7
6
6
6
6
8
6
7
5
“1” is read.
“1” is read.
ADR07
ADR17
Store upper 8 bits of A/D conversion result.
Store upper 8 bits of A/D conversion result.
4
6
5
5
5
5
3
5
2
4
ADR06
ADR16
1
4
4
4
4
3
0
R
R
R
R
1
0
1
0
2
ADR05
ADR15
1
3
3
3
3
7
6
0
5
ADR04
ADR14
2
2
2
2
4
TMP19A61
3
Over RUN
0: Not
1: Generated
Over RUNflag
0: Not
1: Generated
ADR03
ADR13
2
OVR0
flag
generated
OVR1
generated
1
R
1
1
R
1
0
0
1
ADREGxL
0
A/D
conversion
result storage
flag
1: Presence
A/D
conversion
result storage
flag
1: Presence
ADR0RF
ADR1RF
ADR02
ADR12
of
conversion
result
of
conversion
result
0
R
0
0
R
0
0
0