tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 61

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note 1) The above example assumes use of Assembler made by Toshiba. If any third party
(Note 1) Note that general exceptions can be accepted even when interrupts are disabled. So, even
After an interrupt request is accepted, it automatically jumps to the exception handler where the interrupt
vector address is read from INTC IVR and the user program generates the address of the interrupt
handler. As in the example statements presented in Section 6.9.1, “Initialization for Interrupts” the
interrupt vector base address is set to IVR[31:8] so that the IVR value becomes the interrupt vector
address.
After reading the INTC IVR value, the interrupt factor is cleared. If the interrupt factor is cleared before
IVR is read, correct value cannot be read because the IVR value is also cleared.
Typical tasks of the interrupt handler are to save appropriate registers and to process interrupts. If the
shadow register set is enabled (CP0 register SSCR <SSD> = 0), the general purpose register values
other than r26, r27, r28, and r29 (Shadow Register Set number 1 to 7) are automatically saved so the
user program doesn't have to save these. Refer to the separate volume "TX19A Core Architecture" for
details of general purpose registers that are to be automatically saved.
In general, registers other than GPR are dependent on user programs. The Status, EPC, SSCR, HI, LO,
Cause, and Config values of the CP0 register shall be saved as appropriate.
For using multiple interrupts, interrupts are enabled by clearing Status <EXL> of the CP0 register to "0"
after appropriate saving processes.
②Processes to be performed by the exception handler
Example exception handler statement: Exception vector address (interrupt) is 0xBFC0_0400.
VECTOR_INT section code isa32 abs=0xBFC00400
__InterruptVector:
lui
lw
lui
sh
lw
jr
nop
Assembler is used, it may generate syntax errors; you are advised to modify the above
statement according to the Assembler to be used.
when you don't use multiple interrupts, it is desirable to save any general purpose register
and the CP0 register that could be overwritten by general exceptions.
Processes to be performed by the interrupt handler
r26,lo(INTCLR)(r27)
r26,hi(IVR)
r26,lo(IVR)(r26)
r27,hi(INTCLR)
r26,0(r26)
r26
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; Read IVR for interrupt vector address
; Interrupt request is cleared
; Read interrupt handler address from interrupt vector
; Jump to interrupt handler
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