tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 323
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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TMP19A61F10XBG
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13.3.7
13.3.8
Receive FIFO Buffer
Receive FIFO Operation
Receive buffer 2
Receive buffer 1
Receive interrupt
The following example describes the case a 4-byte data stream is received in the half duplex
mode:
SCORFC<7:6>=01: Clears receive FIFO and sets the condition of interrupt generation.
SC0RFC<1:0>=00: Sets the interrupt to be generated at fill level 4.
SC0FCNF<1:0>=10111: Automatically inhibits continued reception after reaching the fill level.
In this condition, 4-byte data reception may be initiated by setting the half duplex transmission
mode and writing “1” to the RXE bit. After receiving 4 bytes, the RXE bit is automatically
cleared and the receive operation is stopped (SCLK is stopped).
Receive FIFO
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by
setting the wake-up function SC0MOD0 <WU> to “1.” In this case, the interrupt INTRX0 will
be generated only when SC0CR <RB8> is set to “1.”
In addition to the double buffer function already described, data may be stored using the
receive FIFO buffer. By setting <CNFG> of the SC0FCNF register and <FDPX1:0> of the
SC0MOD1 register, the 4-byte receive buffer can be enabled. Also, in the UART mode or
I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO
buffer is to be used, be sure to enable the double buffer function.
If data with parity bit is to be received in the UART mode, parity check must be performed
each time a data frame is received.
I/O interface mode with SCLK output:
RBFLL
RXE
Fig. 13.3.8.1 Receive FIFO Operation
1 byte
The number of bytes to be used in the receive FIFO is the same as the
interrupt generation fill level.
TMP19A61 (rev1.0)-13-322
1 byte
2 byte
1 byte
3 byte
2 byte
1 byte
2 byte
3 byte
4 byte
3 byte
2 byte
1 byte
TMP19A61
4 byte
4 byte
3 byte
2 byte
1 byte
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