tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 336

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(0xFFFF_F706)
SC0MOD2
<SWRST1:0>: Overwriting "01" in place of "10" generates a software reset. When this software reset
<WBUF>: This parameter enables or disables the transmit/receive buffers to transmit (in both SCLK
<DRCHG>: Specifies the direction of data transfer in the I/O interface mode. In the UART mode, it is
<TXRUN>: This is a status flag to show that data transmission is in progress.
<RBFLL>: This is a flag to show whether the received double buffers are full or not. When a receive
<TBEMP>: This flag shows that the transmit double buffers are empty. When data in the transmit
<SBLEN>: This specifies the length of stop bit transmission in the UART mode. On the receive side,
(Note)
bit Symbol
Read/Write
After reset
Function
the decision is made using only a single bit regardless of the <SBLEN> setting.
When this bit is set to "1," it indicates that data transmission operation is in progress. If it is
"0," the bit 7 <TBEMP> is set to "1" to indicate that the transmission has been fully
completed and the same <TBEMP> is set to "0" to indicate that the transmit buffer contains
some data waiting for the next transmission.
operation is completed and received data is moved from the receive shift register to the
receive double buffers, this bit changes to "1" while reading this bit changes it to "0."
If double buffering is disabled, this flag is insignificant.
double buffers is moved to the transmit shift register and the double buffers are empty, this
bit is set to "1." Writing data again to the double buffers sets this bit to "0."
If double buffering is disabled, this flag is insignificant.
output/input modes) and receive (in SCLK output mode) data in the I/O interface mode
and to transmit data in the UART. In all other modes, double buffering is enabled
regardless of the <WBUF> setting.
fixed to LSB first.
While data transmission is in progress, any software reset operation must be
executed twice in succession.
is executed, the mode register parameters SC0MOD0 <RXE>, SC0MOD1<TXE>,
SC0MOD2 <TBEMP>, <RBFLL>, and <TXRUN>, control register parameters
SC0CR <OERR>, <PERR>, and <FERR>, and their internal circuits are initialized.
1: Empty
Transmit
buffer
empty flag
0: full
TBEMP
7
1
Fig. 13.4.3 Serial Mode Control Register
1: full
Receive
buffer full
flag
0: Empty
TMP19A61 (rev1.0)-13-335
RBFLL
6
0
1: Start
In
transmissi
on flag
0: Stop
TXRUN
5
0
R/W
STOP
bit
0: 1 bit
1: 2 bits
SBLEN
4
0
Setting
transfer
direction
0: LSB first
1: MSB first
DRCHG
3
0
1: Enable
W-buffer
0: Disable
WBUF
2
0
TMP19A61
Soft reset
Overwrite "01" on "10"
to reset
SWRST1
W
1
0
SWRST0
W
0
0