tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 571

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tmp19a61f10xbg

Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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OUTPUT DATA
INPUT DATA
SCK period
TxD data to SCK rise
TxD data hold after SCK rise
RxD data valid to SCK rise
RxD data hold after SCK rise
SCK period (programmable)
TxD data to SCK rise
TxD data hold after SCK rise
RxD data valid to SCK rise
RxD data hold after SCK rise
(2) Clock-Synchronous 8-Bit SIO mode
SCLK
TxD
TxD
In the table below, the letters x and t represent the fsys periods and φT0 respectively.
The electrical specifications below are for an SCLK signal with a 50% duty cycle.
The letter n denotes the value of n programmed into the SCK (SCL output frequency select)
field in the SBI0CR1.
SCK input mode
SCK output mode
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP19A61 (rev 1.0)-24-570
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
SCY
OSS
OHS
SRD
HSR
SCY
OSS
OHS
SRD
HSR
VALID
1
1
(t
SCY
(t
(t
(t
SCY
SCY
SCY
t
HSR
4x + 10
2x + 30
Min
Min
16x
/2) − (6x +
16x
20)
Equation
Equation
0
0
/2) + 4x
/2) − 20
/2) − 20
t
OHS
Max
Max
VALID
2
2
Min
Min
296
222
296
128
128
17
84
67
0
0
54 MHz
54 MHz
TMP19A61
Max
Max
VALID
3
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3

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