tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 260

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.4.5 Order of Priority of Channels
(Note)
BCR, SAR and DAR values cannot be guaranteed. If a bus error persists, refer to 21.
"List of Functional Registers" appears later in this document.
Concerning the eight channels of the DMAC, the smaller the channel number assigned to each
channel, the higher the priority. If a transfer request is generated to channels 0 and 1 simultaneously,
a transfer request for channel 0 is processed with higher priority and the transfer operation is
performed accordingly. When the transfer request for channel 0 is cleared, the transfer operation for
channel 1 is performed if the transfer request still exists (an internal transfer request is retained if it is
not cleared. The interrupt controller retains an external transfer request if the active state for an
interrupt request assigned to DMA requests in the interrupt controller is set to edge mode. However,
the interrupt controller does not retain an external transfer request if the active state is set to level
mode. If the active state for an interrupt request assigned to DMA requests in the interrupt controller
is set to level mode, it is necessary to continue asserting the interrupt request signal).
If a transfer request is generated when data is being transferred through channel 1, a channel
transition occurs at channel 0, that is, data transfer through channel 1 is temporarily suspended and
data transfer through channel 0 is started. When the transfer request for channel 0 is cleared, data
transfer through channel 1 resumes.
Channel transitions occur upon the completion of data transfers (when the writing of all data in the
DHR has been completed).
Interrupts
Upon completion of a channel operation, the DMAC can generate interrupt requests (INTDMAn:
DMA transfer completion interrupt) to the TX19A processor core with two types of interrupts
available: a normal completion interrupt and an abnormal completion interrupt.
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If a channel operation is completed normally, the NC bit of CSRn is set to "1." If a normal
completion interrupt is authorized for the NIEn bit of the CCRn, the DMAC requests the TX19A
processor core to authorize an interrupt.
If a channel operation is completed abnormally, the AbC bit of CSRn is set to "1." If an
abnormal completion interrupt is authorized for the AbIEn bit of the CCRn, the DMAC requests
the TX19A processor core to authorize an interrupt.
CSRn is set to "1" and the BES or BED bit of CSRn is set to "1."
− A prohibited combination of a device port size and a unit of data to be transferred were set.
− The Str bit of CCRn was set to "1" when the BCRn value was "0."
Completion due to a bus error
If the DMAC operation has been completed abnormally due to a bus error, the AbC bit of
If the DMAC operation has been completed abnormally due to a bus error,
INTDMA0: 0ch, INTDMA1: 1ch, INTDMA1: 2ch, INTDMA1: 3ch
Normal completion interrupt
Abnormal completion interrupt
− A bus error was detected during data transfer.
TMP19A61 (rev1.0)10-259
TMP19A61