tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 67

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

generation
Interrupt
<MLEV>
ILEV
(0xFFFF_E10C) Read/Write
“000”
6.9.4.3
0
(Note 1) This register must be 32-bit accessed.
(Note 2) Be sure to read the IVR value before changing the ILEV value. If the ILEV value is changed
(Note 3) Bit manipulation instructions cannot be used to access this register.
ILEV is the register to control the interrupt level to be used by INTC in notifying interrupt requests to the
TX19A processor core.
Interrupts with interrupt levels not higher than ILEV <CMASK> are suspended. The interrupt priority
level "7" is the highest priority and "1" the lowest. Note that any interrupt with interrupt level 0 is not
suspended.
When a new interrupt is generated, the corresponding interrupt level is stored in <CMASK> and any
previously stored values are incremented in mask levels such that the previous CMASK is saved in
PMASK0 and PMASK0 is saved in PMASK1 and so on. For writing a new value to <CMASK>, set "1" to
<MLEV> and write <CMASK> simultaneously. Writing a new value to <PMASKx> cannot be made.
When <MLEV> is set to "0," the interrupt mask levels in the register shift back to the previous state such
that PMASK0 is moved to CMASK and PMASK1 is moved to PMASK0, and so on. The last <PMASK6>
is set to "000." If it is used in returning from an interrupt process, be sure to set <MLEV> to "0" before
executing the ERET instruction. <MLEV> always reads "0."
PMAS
PMAS
PMAS
before reading IVR, an unexpected interrupt request may be generated.
Interrupt Level Register (ILEV)
Bit Symbol
After Reset
Function
Bit Symbol
Read/Write
After Reset
Function
Bit Symbol
Read/Write
After Reset
Function
Bit Symbol
Read/Write
After Reset
Function
PMAS
PMAS
PMAS
0: Return
1: Change
mask
level
CMASK
MLEV
15
23
31
―
―
―
W
PMAS
PMAS
PMAS
7
0
0
0
0
Table 6.8 Interrupt Level Register
TMP19A61(rev1.0)-6-66
Interrupt mask level (previous) 0
Interrupt mask level (previous) 2
Interrupt mask level (previous) 4
Interrupt mask level (previous) 6
14
22
30
6
PMAS
PMAS
PMAS
PMASK0
PMASK2
PMASK4
PMASK6
000
000
000
000
13
21
29
R
5
PMAS
PMAS
PMAS
12
20
28
4
R
R
PMAS
PMAS
PMAS
19
27
―
11
―
―
―
R
3
0
0
0
0
Interrupt mask level (current)
PMAS
PMAS
PMAS
Interrupt mask level (previous) 1
Interrupt mask level (previous) 3
Interrupt mask level (previous) 5
10
18
26
2
TMP19A61
PMASK1
PMASK3
PMASK5
CMASK
R/W
000
000
000
000
17
25
CMAS
CMAS
CMAS
1
9
interrupt
16
24
0
8
New
level