tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 232

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

BUSCR
(0xFFFFE4C0)
A reset of the TMP19A61 allows the port 4 controller register (P4CR) and the port 4 function register
(P4FC) to be cleared to "0," and the CS signal output is disabled. To output the CS signals, set the
corresponding bits to "1" at the P4FC and the P4CR in that order.
The CS recovery time can be configured in any other areas than the CS setting areas, but CS signals will
not be output.
9.2 Bus Control Register
<ALESEL1:0>: Separate bus and multiplex bus require different settings for ALE width cycle.
<WAITSMP>: Number of WAIT input sampling point can be increased depending on operating
Table 9.3 shows the bus control register.
The bus control register is used for setting ALE width and WAIT sampling point.
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
frequency. However, TMP19A61 adopts 2N: fsys = 4MHz~54MHz.
“0” is read.
7
0
15
23
31
0
0
0
TMP19A61 (rev1.0)-9-231
6
0
14
22
30
0
0
0
Fig. 9.3 Bus Control Register
R
5
0
13
21
29
0
0
0
4
0
12
20
28
0
0
0
“0” is read.
“0” is read.
“0” is read.
R
R
R
3
0
11
19
27
0
0
0
WAITSMP
WAIT
sampling
point
0: 2N
1: -
R/W
2
0
10
18
26
0
0
0
TMP19A61
Multiplex bus
Separate bus
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
1
0
17
25
9
0
0
0
ALESEL
R/W
0
1
16
24
8
0
0
0