tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 340

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(0xFFFF_F708)
(0xFFFF_F709)
0: An interrupt is generated if FIFO is filled up with the data up to the specified level.
1: An interrupt is generated if FIFO is filled up with the data up to the specified level or more when it is read.
0: An interrupt is generated when FIFO is filled up with the data up to the specified level.
1: An interrupt is generated if FIFO is filled up with the data up to the specified level or more when it is read.
SC0RFC
SC0TFC
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Clear RX
FIFO
1: Clear
Clear TX
FIFO
1: Clear
Always
reads "0."
Always
reads "0."
Fig. 13.4.9 Transmit FIFO Configuration Register
RFCS
TFCS
W
W
7
0
7
0
Fig. 13.4.8 Receive FIFO Control Register
Select
interrupt
generation
condition
Select
interrupt
generation
condition
TMP19A61 (rev1.0)-13-339
RFIS
TFIS
R/W
R/W
6
0
6
0
5
0
5
0
4
4
0
0
R
R
3
3
0
0
2
2
0
0
TMP19A61
FIFO fill level to
generate RX interrupts
00: 4 bytes (2 bytes if
full duplex)
01: 1byte
10: 2bytes
11: 3bytes
FIFO fill level to
generate TX interrupts
00: Empty
01: 1byte
10: 2bytes
11: 3bytes
Note: RIL1 is ignored
when FDPX1:0 = 11
(full duplex)
Note: TIL1 is ignored
when FDPX1:0 = 11
(full duplex).
RIL1
TIL1
1
1
0
0
R/W
R/W
RIL0
TIL0
0
0
0
0