tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 349

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive data
read timing
Transmit data
write timing
(INTTX0 interrupt
request)
(INTRX0 interrupt
request)
SCLK0 input
RXD0
TXD0
SCLK input mode
In the SCLK input mode with SC0MOD2 <WBUF> set to "0" and the send double
buffers are disabled (double buffering is always enabled for the receive side), 8-bit
data written in the transmit buffer is output from the TXD0 pin and 8 bits of data is
shifted into the receive buffer when the SCLK input becomes active. The INTTX0
interrupt is generated upon completion of data transmission and the INTRX0 interrupt
is generated at the instant the received data is moved from receive buffer 1 to receive
buffer 2. Note that transmit data must be written into the transmit buffer before the
SCLK input for the next frame (data must be written before the point A in Fig. 13.5.1.6).
As double buffering is enabled for data reception, data must be read before completing
reception of the next frame data.
If SC0MOD2 <WBUF> = "1" and double buffering is enabled for both transmission and
reception, the interrupt INTRX0 is generated at the timing transmit buffer 2 data is
moved to transmit buffer 1 after completing data transmission from transmit buffer 1. At
the same time, the 8 bits of data received is shifted to buffer 1, moved to receive buffer
2, and the INTRX0 interrupt is generated. Upon the SCLK input for the next frame,
transmission from transmit buffer 1 (in which data has been moved from transmit
buffer 2) is started while receive data is shifted into receive buffer 1 simultaneously. If
data in receive buffer 2 has not been read when the last bit of the frame is received, an
overrun error occurs. Similarly, if there is no data written in transmit buffer 2 when
SCLK for the next frame is input, an under-run error occurs.
bit 0
bit 0
<WBUF> = "0" (if double buffering is disabled)
bit 1
bit 1
TMP19A61 (rev1.0)-13-348
bit 5
bit 5
bit 6
bit 6
bit 7
bit 7
A
TMP19A61
bit 0
bit 0
bit 1
bit 1