tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 262

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.6 Timing Diagrams
10.6.1 Dual Address Mode
DMAC operations are synchronous to the rising edges of the internal system clock.
•
•
Fig. 10.16 shows an example of the timing with which 16-bit data is transferred from one
external memory (16-bit width) to another (16-bit width). Data is actually transferred
successively until BCRn becomes "0."
Fig. 10.17 shows an example of the timing if the unit of data to be transferred is set to 16 bits
and the device port size is set to 16 bits.
Continuous transfer
Single transfer (1)
A [23 : 0]
D [15 : 0]
CS0
CS1
RD
WR
A [23 : 0]
D [15 : 0]
CS0
CS1
RD
WR / HWR
Fig. 10.16 Dual address mode (continuous transfer)
Fig. 10.17 Dual address mode (single transfer)
tsys
TMP19A61 (rev1.0)10-261
tsys
Read
Data
Read
Data
Write
Data
Write
Data
TMP19A61