tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 42

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.4
6.5
(Note 1) Address error exceptions (load/store) will not be generated in DMS transfer operations. In
(Note 2) Bus errors (data access) may be generated either by load instructions or by load accesses
An NMI is generated when WDT is counted to an NMI set count or when a bus error area is accessed by
store access including DMA transfer. When an NMI is generated, the status bits <ERL> and <NMI> of
the CP0 register are set to "1" and it jumps to the exception vector address 0xBFC0_0000.
The PC value of NMI generation will be stored in ErrorEPC of the CP0 register. Note that any NMI due to
a bus error upon a store instruction causes an exception that is not synchronized with instruction
sequence. Therefore, the PC value of an instruction being executed at the time of error generation will
be stored instead of the PC value for the instruction that actually caused the error. Upon NMI generation,
when the shadow register set is enabled, SSCR <CSS> will be overwritten by the value of SSCR
<PSS> but the register bank will not be switched because the value of SSCR <CSS> is not updated.
The reason why only the SSCR <PSS> value is updated is because it is necessary to prevent the
register bank from being changed when SSCR <PSS> is overwritten by the value of SSCR <CSS> due
to an ERET instruction executed upon returning from NMI.
The cause of NMI generation can be determined by NMIFLG <WDT> and <WBER> of CG (refer to the
Section 6.11, NMI Flag Register). Refer to the section "Exception Handling, Non-Maskable
Interruptions" of the separate volume "TX19A Core Architecture" for detailed operation upon generation
of NMI.
A general exception will be generated when a specific instruction such as SYSCALL is executed or
when any abnormalities such as an illegal instruction fetch is detected. When a general exception is
generated and if Status <BEV> of the CP0 register is "1," it jumps to the exception vector address
0xBFC0_380. The cause of a general exception can be determined by Cause <ExCode> of the CP0
register.
The PC value at a general exception will be stored in EPC of the CP0 register. Note that any bus error
exception (data access) is not synchronized with instruction sequence so the PC value of an instruction
being executed at the time of error generation will be stored instead of the PC value for the instruction
that actually caused the error. Upon a general exception, when the shadow register set is enabled,
SSCR <CSS> will be overwritten by the value of SSCR <PSS> but the register bank will not be switched
because the value of SSCR <CSS> is not updated. The reason why only the SSCR <PSS> value is
updated is because it is necessary to prevent the register bank from being changed when SSCR <PSS>
is overwritten by the value of SSCR <CSS> due to an ERET instruction executed upon returning from
the exception.
Any illegal address that caused an address error exception (instruction fetch or load/store) or bus error
(instruction fetch/data access) will be stored in BadVAddr of the CP0 register.
Refer to the corresponding sections of "Exception Handling" of the separate volume "TX19A Core
Architecture" for detailed operation upon generation of general exceptions.
Non-maskable Interrupt (NMI)
General Exceptions (Other than Reset Exception and NMI)
DMA transfer, address errors can be detected as configuration errors (CSRx <Conf> of
DMAC).
of DMA transfer operations.
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