tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 448

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.4 Operation Description
The watchdog timer generates the INTWDT interrupt after a lapse of the detection time specified
by the WDMOD <WDTP1, 0> register. Before generating the INTWD interrupt, the binary
counter for the watchdog timer must be cleared to "0" using software (instruction). If the CPU
malfunctions (runs away) due to noise or other disturbances and cannot execute the instruction
to clear the binary counter, the binary counter overflows and the INTWD interrupt is generated.
The CPU is able to recognize the occurrence of a malfunction (runaway) by identifying the
INTWD interrupt and to restore the faulty condition to normal by using a malfunction (runaway)
countermeasure program. Additionally, it is possible to resolve the problem of a malfunction
(runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral
devices.
The watchdog timer begins operation immediately after a reset is cleared.
In STOP mode, the watchdog timer is reset and in an idle state. When the bus is open
( BUSAK = "L"), it continues counting. In IDLE mode, its operation depends on the WDMOD
<I2WDT> setting. Before putting it in IDLE mode, WDMOD <I2WDT> must be set to an
appropriate setting, as required.
Examples:
WDCR
WDMOD
WDMOD
WDCR
To clear the binary counter
To set the detection time of the watchdog timer to 2
To disable the watchdog timer
← 0 1 0 0 1 1 1 0
← 1 0 1
← 0
← 1 0 1 1 0 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
− − − − − − −
TMP19A61
− − − − −
(rev1.0)
Writes the clear code
Clears WDTE
Writes the disable code
-17-447
to “0”.
(4EH).
18
(B1H).
/f
SYS
TMP19A61