tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 318

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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1) Division by an integer (divide by N):
2) For divide by N + (16-K)/16 (only for UART mode):
(Note)
2) I/O interface mode
Example baud rate setting
The highest baud rate will be generated when φ T1 is 13.5 MHz. The divide ratio can
be set to 1 if double buffer is used and the resulting output baud rate will be 6.75 Mbps.
(If double buffering is not used, the highest baud rate will be 3.375 Mbps applying the
divide ratio of “2”).
Clock condition
Clock condition
Selecting fc = 54MHz for fperiph, setting φ T0 to fperiph/16, using the baud rate
generator input clock φ T1, setting the divide ratio N (BR0CR<BR0S3:0>) = 4, and
setting BR0CR<BR0ADDE> = “0,” the resulting baud rate in the UART mode is
calculated as follows:
Selecting fc = 54MHz for fperiph, setting φ T0 to fperiph/16, using the baud rate
generator input clock φ T1, setting the divide ratio N (BR0CR<BR0S3:0>)=4, setting K
(BR0ADD<BR0K3:0>)=14, and selecting BR0CR<BR0ADDE>=1, the resulting baud
rate is calculated as follows:
Baud rate =
= 54 × 10
Baud rate =
= 54 × 10
Baud rate =
The divide by (N + (16-K)/16) function is inhibited and thus BR0ADD
<BR0K3:0> is ignored.
6
6
÷ 32 ÷ ( 4 +
÷ 32 ÷ 4 ÷ 16 = 26367 (bps)
fc/32
Frequency
4
TMP19A61 (rev1.0)-13-317
4
+
Baud
fc/32
÷ 16
(16-14)
rated
16
divided
) ÷ 16 = 25568 (bps)
generator
System clock
High-speed clock gear:1x (fc)
Prescaler clock
System clock
High-speed clock gear:1x (fc)
Prescaler clock
÷
16
2
by the
16
input
divide
clock
ratio
÷ 2
:High-speed (fc)
:fperiph/16 (fperiph = fsys)
:High-speed (fc)
:fperiph/16 (fperiph = fsys)
TMP19A61