tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 233
tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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10. DMA Controller (DMAC)
10.1 Features
The TMP19A61 has a built-in 8-channel DMA Controller (DMAC).
The DMAC of the TMP19A61 has the following features:
(1) DMA with 8 independent channels
(2) Two types of requests for bus control authority: With and without snoop requests
(3) Transfer mode: Dual address mode
(4) Transfer devices: Memory space transfer
(5) Device size: 32-bit memory (8 or 16 bits can be specified using the CS/WAIT controller); I/O of 8,
(6) Address changes: Increase, decrease, fixed, irregular increase, irregular decrease
(7) Channel priority: Fixed (in ascending order of channel numbers)
(8) Endian switchover function
Requests given by the DREQ pin: Level mode
Transfer requests: Internal requests (software initiated)/external requests (external interrupts,
interrupt requests given by internal peripheral I/Os, and requests given by the DREQ pin)
(eight interrupt factors, 0: INTDMA0 through INTDMA7)
16 or 32 bits
TMP19A61 (rev1.0)10-232
TMP19A61
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