tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 209

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(4) Recovery time
If access to external areas occurs consecutively, a dummy cycle can be inserted for
recovery time.
A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle
insertion setting can be made in the chip selector and wait controller registers,
BmnCS<BnWCV> (write recovery cycle) and <BnRCV> (read recovery cycle). As for the
number of dummy cycles, one, two or four system clocks (internal) can be specified for
each block. Fig. 8.9 shows the timing of recovery time insertion.
Fig. 8.9 Timing of Recovery Time Insertion in Separate Bus Mode
CS
A［23:0］
RD
WR
CS
A［23:0］
RD
WR
TMP19A61(rev1.0)-8-208
No recovery cycle
address
address
tsys
tsys
1 recovery cycle
next address
next address
2 recovery cycles
TMP19A61