tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 211

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.4
CSn
A [23 : 16]
AD [15 : 0]
ALE
RD
External Bus Operations (Multiplexed Bus Mode)
CSn
A [23 : 16]
AD [15 : 0]
ALE
WR
This section describes various bus timing values. The timing diagram shown below assumes
that the address buses are A23 through A16 and that the address/data buses are AD15
through AD0.
(1) Basic bus operation
wait can be inserted as mentioned later. The basic clock of an external bus cycle is the
same as the internal system clock.
Fig. 8.11 shows read bus timing and Fig. 8.12 shows write bus timing. If internal areas
are accessed, address buses remain unchanged and the ALE does not output latch pulse
as shown in these figures. Additionally, address/data buses are in a state of high
impedance and control signals such as RD and
The external bus cycle of the TMP19A61 basically consists of three clock pulses and a
Fig. 8.11 Read Operation Timing Diagram
Fig. 8.12 Write Operation Timing Diagram
ｔsys
TMP19A61(rev1.0)-8-210
ADR
ADR
ｔsys
External access
External area
DATA
DATA
WR
No output of RD
Upper address HOLD
Output Hi − Z
No output of ALE
Internal access
Upper address HOLD
do not become active.
No output of WR
No output of ALE
Internal
Output of Hi − Z
area
TMP19A61