tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 271

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Specification
External pins
Specification
External pins
(addresses)
(addresses)
Register
Register
Internal
Internal
signals
signals
names
names
External clock/
capture trigger input
pins
Timer flip-flop output
pin
Timer for capture
triggers
Timer RUN register
Timer control register
Timer mode register
Timer flip-flop control
register
Timer status register
Timer up counter
register
Timer register
Capture register
External clock/
capture trigger input
pins
Timer flip-flop output
pin
Timer for capture
triggers
Timer RUN register
Timer control register
Timer mode register
Timer flip-flop control
register
Timer status register
Timer up counter
register
Timer register
Capture register
Channel
Channel
Table 11.1 Differences in the Specifications of TMRB Modules (2/5)
TB8IN0 (
TB8IN1 (
TB08RUN (0xFFFF_F280)
TB08CR (0xFFFF_F281)
TB08MOD (0xFFFF_F282)
TB08FFCR 0xFFFF_F283)
TB08ST (0xFFFF_F284)
TB08UCL
TB08UCH
TB08RG0L(0xFFFF_F288)
TB08RG0H(0xFFFF_F289)
TB08RG1L(0xFFFF_F28A)
TB08RG1H(0xFFFF_F28B)
TB08CP0L 0xFFFF_F28C)
TB08CP0H(0xFFFF_F28D)
TB08CP1L(0xFFFF_F28E)
TB08CP1H(0xFFFF_F28F)
TBCIN0 (
TBCIN1 (
TB0CRUN (0xFFFF_F2C0)
TB0CCR (0xFFFF_F2C1)
TB0CMOD (0xFFFF_F2C2)
TB0CFFCR (0xFFFF_F2C3)
TB0CST (0xFFFF_F2C4)
TB0CUCL
TB0CUCH
TB0CRG0L (0xFFFF_F2C8)
TB0CRG0H (0xFFFF_F2C9)
TB0CRG1L (0xFFFF_F2CA)
TB0CRG1H (0xFFFF_F2CB)
TB0CCP0L (0xFFFF_F2CC)
TB0CCP0H (0xFFFF_F2CD)
TB0CCP1L (0xFFFF_F2CE)
TB0CCP1H (0xFFFF_F2CF)
TMRB0C
TMRB08
shared with
shared with
shared with
shared with
TB1OUT
TB1OUT
-
-
TMP19A61 (rev 1.0)11-270
PB0)
PB1)
PC0)
PC1)
TB9IN0 (
TB9IN1 (
TB09RUN (0xFFFF_F290)
TB09CR (0xFFFF_F291)
TB09MOD (0xFFFF_F292)
TB09FFCR(0xFFFF_F293)
TB09ST (0xFFFF_F294)
TB09UCL
TB09UCH
TB09RG0L(0xFFFF_F298)
TB09RG0H(0xFFFF_F299)
TB09RG1L(0xFFFF_F29A)
TB09RG1H(0xFFFF_F29B)
TB09CP0L(0xFFFF_F29C)
TB09CP0H(0xFFFF_F29D)
TB09CP1L(0xFFFF_F29E)
TB09CP1H(0xFFFF_F29F)
TBDIN0 (
TB0DRUN (0xFFFF_F2D0)
TB0DCR (0xFFFF_F2D1)
TB0DMOD (0xFFFF_F2D2)
TB0DFFCR (0xFFFF_F2D3)
TB0DST (0xFFFF_F2D4)
TB0DUCL
TB0DUCH
TB0DRG0L (0xFFFF_F2D8)
TB0DRG0H (0xFFFF_F2D9)
TB0D0RG1L (0xFFFF_F2DA)
TB0DRG1H (0xFFFF_F2DB)
TB0DCP0L (0xFFFF_F2DC)
TB0DCP0H (0xFFFF_F2DD)
TB0DCP1L (0xFFFF_F2DE)
TB0DCP1H (0xFFFF_F2DF)
TMRB0D
TMRB09
shared with
shared with
shared with
TB1OUT
TB1OUT
-
-
PB2)
PB3)
PC2) TBEIN0 (
TBAIN0 (
TBAIN1 (
TB0ARUN (0xFFFF_F2A0)
TB0ACR (0xFFFF_F2A1)
TB0AMOD (0xFFFF_F2A2)
TB0AFFCR(0xFFFF_F2A3)
TB0AST (0xFFFF_F2A4)
TB0AUCL
TB0AUCH
TB0ARG0L (0xFFFF_F2A8)
TB0ARG0H (0xFFFF_F2A9)
TB0ARG1L (0xFFFF_F2AA)
TB0ARG1H (0xFFFF_F2AB)
TB0ACP0L (0xFFFF_F2AC)
TB0ACP0H (0xFFFF_F2AD)
TB0ACP1L (0xFFFF_F2AE)
TB0ACP1H (0xFFFF_F2AF)
TB0ERUN (0xFFFF_F2E0)
TB0ECR (0xFFFF_F2E1)
TB0EMOD (0xFFFF_F2E2)
TB0EFFCR(0xFFFF_F2E3)
TB0EST (0xFFFF_F2E4)
TB0EUCL
TB0EUCH
TB0ERG0L (0xFFFF_F2E8)
TB0ERG0H (0xFFFF_F2E9)
TB0ERG1L (0xFFFF_F2EA)
TB0ERG1H (0xFFFF_F2EB)
TB0ECP0L (0xFFFF_F2EC)
TB0ECP0H (0xFFFF_F2ED)
TB0ECP1L (0xFFFF_F2EE)
TB0ECP1H (0xFFFF_F2EF)
TMRB0A
TMRB0E
shared with
shared with
shared with
TB1OUT
TB1OUT
-
-
PB4)
PB5)
PC3)
TMP19A61
TBBIN0 (
TBBIN1 (
TB0BRUN (0xFFFF_F2B0)
TB0BCR (0xFFFF_F2B1)
TB0BMOD (0xFFFF_F2B2)
TB0BFFCR (0xFFFF_F2B3)
TB0BST (0xFFFF_F2B4)
TB0BUCL
TB0BUCH
TB0BRG0L (0xFFFF_F2B8)
TB0BRG0H (0xFFFF_F2B9)
TB0BRG1L (0xFFFF_F2BA)
TB0BRG1H (0xFFFF_F2BB)
TBBCP0L (0xFFFF_F2BC)
TBBCP0H (0xFFFF_F2BD)
TBBCP1L (0xFFFF_F2BE)
TBBCP1H (0xFFFF_F2BF)
TBFIN0 (
TB0FRUN (0xFFFF_F2F0)
TB0FCR (0xFFFF_F2F1)
TB0FMOD (0xFFFF_F2F2)
TB0FFFCR (0xFFFF_F2F3)
TB0FST (0xFFFF_F2F4)
TB0FUCL
TB0FUCH
TB0FRG0L (0xFFFF_F2F8)
TB0FRG0H (0xFFFF_F2F9)
TB0FRG1L (0xFFFF_F2FA)
TB0FRG1H (0xFFFF_F2FB)
TB0FCP0L (0xFFFF_F2FC)
TB0FCP0H (0xFFFF_F2FD)
TB0FCP1L (0xFFFF_F2FE)
TB0FCP1H (0xFFFF_F2FF)
TMRB0B
TMRB0F
shared with
shared with
shared with
TB1OUT
TB1OUT
-
-
PB6)
PB7)
PC7)