tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 408

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SCL pin
Write to SBI0DBR
SDA pin
<PIN>
INTSBI interrupt
request
SCL
SDA
<PIN>
INTSBI interrupt
request
INTSBI interrupt
Receiver mode (<TRX> = "0")
If the next data to be transmitted has eight bits, the transmit data is written into SBI0DBR. If
the data has different length, <BC2:0> and <ACK> are programmed and the received data
is read from SBI0DBR to release the SCL line.
transmission of a slave address is undefined.) On reading the data, <PIN> is set to "1 and
the serial clock is output to the SCL pin to transfer the next data word. In the last bit, when
the acknowledgment signal becomes the "L" level, "0" is output to the SDA pin.
After that, the INTSBI interrupt request is generated, and <PIN> is cleared to "0," pulling
the SCL pin to the "L" level. Each time the received data is read from SBI0DBR, one-word
transfer clock and an acknowledgement signal are output.
if MST = 0
Then go to the slave-mode processing
if TRX = 0
Then go to the receiver-mode processing
if LRB = 0
Then go to processing for generating the stop condition
End of interrupt processing
(Note)
SBI0CR1 ← X X X X 0 X X X
SBI0DBR ← X X X X X X X X
Fig. 15.6.3.1 <BC2:0> = "000" and <ACK> = "1" (Transmitter Mode)
Fig. 15.6.3.2 <BC2:0> = "000" and <ACK> = "1" (Receiver Mode)
D7
D7
Read the received data
X: Don’t care
1
1
D6
D6
2
2
TMP19A61
D5
D5
3
3
D4
(
D4
rev1.0
4
4
Specifies the number of bits to be transmitted and specify
whether ACK is required.
Writes the transmit data.
)
D3
D3
-15-407
5
5
D2
D2
6
6
(The data read immediately after
D1
D1
7
7
D0
D0
TMP19A61
8
8
Master to slave
Slave to master
ACK
Master to slave
Slave to master
ACK
9
9
Acknowledgment
signal from receiver
Acknowledgment
signal to transmitter
Next D7