tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 52

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(Note) Be sure to read the IVR value before attempting to change the ILEV value. If the ILEV value is
(1) Interrupts
external pins
(2)Other interrupts
6.8.3
6.8.4
Each of interrupt factors has its own interrupt detection sequence as described in Table 6.4. Upon
detection, an interrupt request is notified to INTC for priority arbitration and then notified to the TX19A
processor core. Refer to Table 6.8 for the detection level available for each interrupt factor.
INT0~INTB
Interrupt
1.
2.
3.
changed before reading IVR, an unexpected interrupt request may be generated.
Detecting Interrupt Requests
Interrupt Priority Arbitration
Seven levels of interrupt priority
Interrupt Level Notification
INTC Register Update
Each of interrupt factors can be individually set to one of the seven interrupt priority levels
by INTC.
The interrupt level to be applied is set by IMCxx <ILxxx> of INTC. The higher the interrupt
level set, the higher the priority. If the value is set to "000" meaning interrupt level of 0, no
interrupts will be generated by the factor. Also note that any factors of interrupt level 0 are
not suspended.
When an interrupt request is generated, INTC compares the interrupt level with the mask
level. If the interrupt level is higher than the mask level set in ILEV <CMASK>, it notifies the
TX19A processor of the interrupt request.
If more than one interrupts are generated at the same time, the interrupts are notified in
accordance with the priority order of these interrupt levels. If more than one interrupts of a
same interrupt level are generated at the same time, these interrupts are notified in the
order of the interrupt number as listed in Table 6.2.
When an interrupt request of the same interrupt factor is received again before the previous
interrupt has been cleared, only the first interrupt can be accepted.
When an interrupt request is accepted by the TX19A core, the highest interrupt level at that
point in time will be set to ILEV <CMASK> and the corresponding vector value is set to IVR.
Once CMASK and IVR are set, any interrupt with a higher interrupt level cannot update
them or cause notification to the core until the IVR value is read.
from
Detected by
Table 6.4 Location of Interrupt Request Detection
INTC
INTC
CG
TMP19A61(rev1.0)-6-51
PORT
PORT
Peripheral circuit
Core
→
→
CG(detection)
INTC (detection/ arbitration)
Interrupt Notification Route
→
INTC (detection/ arbitration)
→
INTC(arbitration)
→
TMP19A61
TX19A Core
→
TX19A Core
→
TX19A