tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 540

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ROMSEC1<RSECON> write
ROMSEC1<RSECON>
ROM data protecting is released by setting ROM protecting register ROMSEC1<RSECON>“0" and writing
protecting code “0x0000_003D" in ROM protecting lock register ROMSEC2. Moreover, ROM data
protecting
ROMSEC1<RSECON>“1" and writing protecting code “0x0000_003D" in ROM protecting lock register
ROMSEC2.
Please note the reading data is different from original write data since the ROMSEC2 register is only for
writing.
ROM protecting register is initialized by power-on reset, and the value doesn't change by a normal reset.
23.5.2 ROM data Protecting
ROM data protecting becomes effective at ROM protecting register ROMSEC1<RSECON>=“1" with the
flash protected.
After releasing reset, the RSECON bit is initialized by "1". The flash protecting is sure to enter the state
of ROM data protecting in the mask version after releasing reset because it is always effective. The
condition whether to enter the state of ROM data protecting is defined depending on the state of the
flash protecting.
When ROM protecting register is rewritten with ROM data protected, rewriting can be executed only
from the program put on internal ROM. Therefore, it is necessary to prepare the release program of
ROM data protecting on internal ROM.
RSECON bit consists of the 2 data paths to prevent the unintended release due to overdrive.
See the schematic shown below.
CLK
function
can
The access other than internal ROM is
disabled under ROM data protecting.
be
D
Reset
SD
TMP19A61 (rev1.0) 23-539
ROMSEC2 = 0x0000_003D
set
Q
again
by
similarly
ROMSEC1<RSECON> read
Power on reset
D
SD
setting
Q
ROM
TMP19A61
protecting
ROM protecting
register