tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 264

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

HWR
R/W
CSn
Internal system clock
ALE
A [23:16]
AD [15:0]
Internal system clock
DREQn
DACKn
ALE
A [23:16]
AD [15:0]
RD
WR
HWR
CSn
R/W
DREQn
DACKn
RD
WR
10.6.2 DREQn-Initiated Transfer Mode
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•
Fig. 10.19 shows two timing cycles in which 16-bit data is transferred twice from internal RAM
to external memory (16-bit width).
Fig. 10.20 shows two timing cycles in which 16-bit data is transferred twice from external
memory (16-bit width) to internal RAM.
Data transfer from internal RAM to external memory (multiplexed bus, 5-wait insertion,
Data transfer from external memory to internal RAM (multiplexed bus, 5-wait insertion,
level mode)
level mode)
(7+α) clock
(7+α) clock
Fig. 10-20 Level Mode (from External Memory to Internal RAM)
Fig. 10.19 Level Mode (from Internal RAM to External Memory)
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Add
TMP19A61 (rev1.0)10-263
5 waits
5 waits
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Add
Data
Data
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Add
Data
TMP19A61
Data