tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 220

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

9. The Chip Selector and Wait Controller
9.1.1 Base and Mask Address Setting Registers
9.1 Specifying Address Spaces
The TMP19A61 can be connected to external devices (I/O devices, ROM and SRAM).
6-block address spaces (CS0 through CS5) can be established in the TMP19A61 and three
parameters can be specified for each address and other address spaces: data bus width, the
number of waits and the number of dummy cycles.
spaces CS0 through CS5. These pins generate chip selector signals (for ROM and SRAM) to
each space when the CPU designates an address in which spaces CS0 through CS5 are selected.
For chip selector signals to be generated, however, the port 4 controller register (P4CR) and the
port 4 function register (P4FC) must be set appropriately.
The specification of the spaces CS0 through CS5 is to be performed with a combination of base
addresses (BAn, n=0 to 5) and mask addresses (MAn, n=0 to 5) using the base and mask address
setting registers (BMA0 through BMA3).
Meanwhile, master enable, data bus width, the number of waits and the number of dummy cycles
for each address space are specified in the chip selector and wait controller registers (B01CS,
B23CS and B45CS).
A bus wait request pin ( WAIT ) is provided as an input pin to control the status of these settings.
Spaces CS0 through CS5 are specified using the base and mask address setting registers (BMA0
through BMA5).
In each bus cycle, a comparison is made to see if each address on the bus is located in the space
CS0 through CS5. If the result of a comparison is a match, it is considered that the designated CS
space has been accessed. Then chip selector signals are output from pins
The operations specified by the chip selector and wait controller registers (B01CS, B23CS and
B45CS) are executed (refer to "9.2 The Chip Selector and Wait Controller Register").
CS0 through
Fig. 9.1.1 through Fig. 9.1.3 show base and mask address setting registers. For base
addresses (BA0 through BA5), a start address in the space CS0 through CS5 is specified. In
each bus cycle, the chip selector and wait controller compare values in their registers with
addresses though those addresses with address bits masked by the mask address (MA0
through MA5) are not compared. The size of an address space is determined by the mask
address setting.
(1) Base addresses
Base address BAn specifies the higher-order 16 bits (A31 through A16) of the start address.
The lower-order 16 bits (A15 to A0) of the start address are always set to "0." Therefore, the
start address begins with 0x0000_0000H and increases in 64 k byte units.
(2) Mask addresses
Mask address (MAn) specifies which address bit value is to be compared. The address on the
bus that corresponds to the bit for which "0" is written on the address mask MAn is to be
included in address comparison to determine if the address is in the area of the CS0 to CS5
spaces. The bit in which "1" is written is not included in address comparison.
Fig. 9.1.4 shows the relationship between the start address and the BAn value.
CS
5
(also used as P40 through P45) are the output pins corresponding to
TMP19A61 (rev1.0)-9-219
TMP19A61
CS
0
through
CS .
5